From c486e3ef342ea7bace4c124f905bfa154f47dacc Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 17 Jan 2013 16:31:58 +0100 Subject: radeonsi: Enable tiling for depth/stencil resources. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling it for all resources still seems to cause problems, but depth/stencil buffers are always accessed with tiling by the DB block. Also, stick to 1D tiling for now. Getting 2D tiling to work properly will require substantial changes in libdrm_radeon and possibly the kernel as well. Reviewed-by: Christian König Signed-off-by: Michel Dänzer --- src/gallium/drivers/radeonsi/r600_texture.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index de46640d7e4..580af540f74 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -521,14 +521,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; int r; -#if 0 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && - !(templ->bind & PIPE_BIND_SCANOUT)) { + !(templ->bind & PIPE_BIND_SCANOUT) && + util_format_is_depth_or_stencil(templ->format)) { if (permit_hardware_blit(screen, templ)) { - array_mode = V_009910_ARRAY_2D_TILED_THIN1; + array_mode = V_009910_ARRAY_1D_TILED_THIN1; } } -#endif r = r600_init_surface(rscreen, &surface, templ, array_mode, templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); -- cgit v1.2.3