From 6a5a4d59ce63aa1fa14d3dd6c50169c532424b6d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 11 Sep 2012 15:24:32 -0400 Subject: radeon/llvm: Fix lowering of vbuild Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns. --- src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 2 - src/gallium/drivers/radeon/AMDGPUISelLowering.h | 2 - src/gallium/drivers/radeon/AMDGPUInstructions.td | 10 +++- src/gallium/drivers/radeon/AMDILISelLowering.cpp | 68 ----------------------- src/gallium/drivers/radeon/AMDILInstrInfo.td | 6 -- src/gallium/drivers/radeon/R600Instructions.td | 20 +++---- src/gallium/drivers/radeon/SIInstructions.td | 4 +- 7 files changed, 19 insertions(+), 93 deletions(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 0a70164fcbf..59daf77503e 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -88,7 +88,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) // AMDIL DAG lowering case ISD::SDIV: return LowerSDIV(Op, DAG); case ISD::SREM: return LowerSREM(Op, DAG); - case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); case ISD::BRCOND: return LowerBRCOND(Op, DAG); // AMDGPU DAG lowering @@ -336,7 +335,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const NODE_NAME_CASE(CALL); NODE_NAME_CASE(UMUL); NODE_NAME_CASE(DIV_INF); - NODE_NAME_CASE(VBUILD); NODE_NAME_CASE(RET_FLAG); NODE_NAME_CASE(BRANCH_COND); diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h index 4c100da9690..a6d2a50d11b 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h @@ -90,7 +90,6 @@ private: SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; @@ -105,7 +104,6 @@ enum // AMDIL ISD Opcodes FIRST_NUMBER = ISD::BUILTIN_OP_END, MAD, // 32bit Fused Multiply Add instruction - VBUILD, // scalar to vector mov instruction CALL, // Function call based on a single integer UMUL, // 32bit unsigned multiplication DIV_INF, // Divide with infinity returned on zero divisor diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 6f47445b07c..3e850ebe184 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -154,9 +154,13 @@ class Insert_Element ; // Vector Build pattern -class Vector_Build : Pat < - (IL_vbuild elemClass:$src), - (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x) +class Vector_Build : Pat < + (vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y), + (elemType elemClass:$z), (elemType elemClass:$w))), + (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG + (vecType (IMPLICIT_DEF)), elemClass:$x, sel_x), elemClass:$y, sel_y), + elemClass:$z, sel_z), elemClass:$w, sel_w) >; // bitconvert pattern diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index 6983b40a780..993025c3d47 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -162,7 +162,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() { MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; - setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); setOperationAction(ISD::SDIVREM, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand); @@ -217,7 +216,6 @@ void AMDGPUTargetLowering::InitAMDILLowering() setOperationAction(ISD::BRIND, MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); - setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom); // Use the default implementation. setOperationAction(ISD::ConstantFP , MVT::f32 , Legal); @@ -350,72 +348,6 @@ AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const return DST; } -SDValue -AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const -{ - EVT VT = Op.getValueType(); - SDValue Nodes1; - SDValue second; - SDValue third; - SDValue fourth; - DebugLoc DL = Op.getDebugLoc(); - Nodes1 = DAG.getNode(AMDGPUISD::VBUILD, - DL, - VT, Op.getOperand(0)); -#if 0 - bool allEqual = true; - for (unsigned x = 1, y = Op.getNumOperands(); x < y; ++x) { - if (Op.getOperand(0) != Op.getOperand(x)) { - allEqual = false; - break; - } - } - if (allEqual) { - return Nodes1; - } -#endif - switch(Op.getNumOperands()) { - default: - case 1: - break; - case 4: - fourth = Op.getOperand(3); - if (fourth.getOpcode() != ISD::UNDEF) { - Nodes1 = DAG.getNode( - ISD::INSERT_VECTOR_ELT, - DL, - Op.getValueType(), - Nodes1, - fourth, - DAG.getConstant(7, MVT::i32)); - } - case 3: - third = Op.getOperand(2); - if (third.getOpcode() != ISD::UNDEF) { - Nodes1 = DAG.getNode( - ISD::INSERT_VECTOR_ELT, - DL, - Op.getValueType(), - Nodes1, - third, - DAG.getConstant(6, MVT::i32)); - } - case 2: - second = Op.getOperand(1); - if (second.getOpcode() != ISD::UNDEF) { - Nodes1 = DAG.getNode( - ISD::INSERT_VECTOR_ELT, - DL, - Op.getValueType(), - Nodes1, - second, - DAG.getConstant(5, MVT::i32)); - } - break; - }; - return Nodes1; -} - SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const { diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td index 779566d4bf3..f8771afa180 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.td +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td @@ -124,12 +124,6 @@ def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>; def IL_umul : SDNode<"AMDGPUISD::UMUL" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; -//===----------------------------------------------------------------------===// -// Vector functions -//===----------------------------------------------------------------------===// -def IL_vbuild : SDNode<"AMDGPUISD::VBUILD", SDTIL_GenVecBuild, - []>; - //===--------------------------------------------------------------------===// // Custom Pattern DAG Nodes //===--------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 7e2deac8b00..8d2f137434c 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -1239,23 +1239,23 @@ def : Extract_Element ; def : Extract_Element ; def : Extract_Element ; -def : Insert_Element ; -def : Insert_Element ; -def : Insert_Element ; -def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; def : Extract_Element ; def : Extract_Element ; def : Extract_Element ; def : Extract_Element ; -def : Insert_Element ; -def : Insert_Element ; -def : Insert_Element ; -def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; -def : Vector_Build ; -def : Vector_Build ; +def : Vector_Build ; +def : Vector_Build ; // bitconvert patterns diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 1f3b92de6b3..05665629428 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -1058,8 +1058,8 @@ def : Insert_Element ; def : Insert_Element ; def : Insert_Element ; -def : Vector_Build ; -def : Vector_Build ; +def : Vector_Build ; +def : Vector_Build ; def : BitConvert ; def : BitConvert ; -- cgit v1.2.3