From 379e3382e8631fdd15c28c6643512205483e7b99 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sun, 23 Aug 2015 13:05:53 +0200 Subject: radeonsi: remove no-op 32-bit masking Reviewed-by: Alex Deucher --- src/gallium/drivers/radeon/r600_query.c | 4 ++-- src/gallium/drivers/radeonsi/si_compute.c | 2 +- src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- src/gallium/drivers/radeonsi/si_dma.c | 4 ++-- src/gallium/drivers/radeonsi/si_shader.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c index 65339bbb66f..deeae0a6a65 100644 --- a/src/gallium/drivers/radeon/r600_query.c +++ b/src/gallium/drivers/radeon/r600_query.c @@ -341,8 +341,8 @@ static void r600_emit_query_predication(struct r600_common_context *ctx, struct while (results_base < qbuf->results_end) { radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); - radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL); - radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF)); + radeon_emit(cs, va + results_base); + radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF)); r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ, RADEON_PRIO_MIN); results_base += query->result_size; diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index d4fe5653687..0cdecd6da79 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -362,7 +362,7 @@ static void si_launch_grid( shader_va += pc; #endif si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); - si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff); + si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8); si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40); si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 890be071596..b74c893c7d5 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -426,7 +426,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) va = rbuffer->gpu_address + offset; /* Fill in T# buffer resource description */ - desc[0] = va & 0xFFFFFFFF; + desc[0] = va; desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride); diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 7a0076e7aa9..1a7eeaecf9e 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -86,8 +86,8 @@ static void si_dma_copy_buffer(struct si_context *ctx, for (i = 0; i < ncopy; i++) { csize = size < max_csize ? size : max_csize; cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize); - cs->buf[cs->cdw++] = dst_offset & 0xffffffff; - cs->buf[cs->cdw++] = src_offset & 0xffffffff; + cs->buf[cs->cdw++] = dst_offset; + cs->buf[cs->cdw++] = src_offset; cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff; cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff; dst_offset += csize << shift; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 98b42890f7d..ab5b3ee9ce9 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -3781,7 +3781,7 @@ void si_shader_apply_scratch_relocs(struct si_context *sctx, uint64_t scratch_va) { unsigned i; - uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff; + uint32_t scratch_rsrc_dword0 = scratch_va; uint32_t scratch_rsrc_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64); -- cgit v1.2.3