From 3308f4b81a14ce14aa0efdd3d6a2383c4925fea3 Mon Sep 17 00:00:00 2001 From: Timothy Arceri Date: Thu, 23 Nov 2017 12:59:01 +1100 Subject: radeonsi: create get_tcs_tes_buffer_address helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be shared between the NIR and TGSI backends. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_shader.c | 44 +++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 12 deletions(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 5da9ec0bf54..00770547499 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -977,6 +977,34 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx, return base_addr; } +/* This is a generic helper that can be shared by the NIR and TGSI backends */ +static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices( + struct si_shader_context *ctx, + LLVMValueRef vertex_index, + LLVMValueRef param_index, + unsigned param_base, + ubyte *name, + ubyte *index, + bool is_patch) +{ + unsigned param_index_base; + + param_index_base = is_patch ? + si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) : + si_shader_io_get_unique_index(name[param_base], index[param_base]); + + if (param_index) { + param_index = LLVMBuildAdd(ctx->ac.builder, param_index, + LLVMConstInt(ctx->i32, param_index_base, 0), + ""); + } else { + param_index = LLVMConstInt(ctx->i32, param_index_base, 0); + } + + return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), + vertex_index, param_index); +} + static LLVMValueRef get_tcs_tes_buffer_address_from_reg( struct si_shader_context *ctx, const struct tgsi_full_dst_register *dst, @@ -987,7 +1015,7 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg( struct tgsi_full_src_register reg; LLVMValueRef vertex_index = NULL; LLVMValueRef param_index = NULL; - unsigned param_index_base, param_base; + unsigned param_base; reg = src ? *src : tgsi_full_src_register_from_dst(dst); @@ -1025,19 +1053,11 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg( } else { param_base = reg.Register.Index; - param_index = ctx->i32_0; } - param_index_base = reg.Register.Dimension ? - si_shader_io_get_unique_index(name[param_base], index[param_base]) : - si_shader_io_get_unique_index_patch(name[param_base], index[param_base]); - - param_index = LLVMBuildAdd(ctx->ac.builder, param_index, - LLVMConstInt(ctx->i32, param_index_base, 0), - ""); - - return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), - vertex_index, param_index); + return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index, + param_index, param_base, + name, index, !reg.Register.Dimension); } static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base, -- cgit v1.2.3