From 32dd8d59b6d1b6828e16e854d589d0f04536da14 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Wed, 1 Mar 2017 11:09:30 -0500 Subject: nvc0: increase alignment to 256 for texture buffers on fermi When binding as textures, the alignment can be 16. However when binding as an image, the address has to be aligned to 256. (Also when binding as an RT, but that can't happen with GL or current gallium APIs.) Reported-by: Roy Spliet Signed-off-by: Ilia Mirkin Acked-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 25c60f92ce3..643eb4305f8 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -147,7 +147,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - return 16; /* 256 for binding as RT, but that's not possible in GL */ + if (class_3d < NVE4_3D_CLASS) + return 256; /* IMAGE bindings require alignment to 256 */ + return 16; case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: return 16; case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: -- cgit v1.2.3