From 692f2640ab0c4c923a5ba12ff8526d2d1a3eefb1 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 26 Oct 2016 17:43:19 +0200 Subject: gallium/radeon: replace radeon_surf_info::dcc_enabled with num_dcc_levels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gallium/winsys') diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 45edcc28734..8c57287f073 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -218,7 +218,6 @@ static int compute_level(struct amdgpu_winsys *ws, /* Clear DCC fields at the beginning. */ surf_level->dcc_offset = 0; - surf_level->dcc_enabled = false; /* The previous level's flag tells us if we can use DCC for this level. */ if (AddrSurfInfoIn->flags.dccCompatible && @@ -236,7 +235,7 @@ static int compute_level(struct amdgpu_winsys *ws, if (ret == ADDR_OK) { surf_level->dcc_offset = surf->dcc_size; surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize; - surf_level->dcc_enabled = true; + surf->num_dcc_levels = level + 1; surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); } @@ -488,6 +487,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, } } + surf->num_dcc_levels = 0; surf->surf_size = 0; surf->dcc_size = 0; surf->dcc_alignment = 1; -- cgit v1.2.3