From 6067a30838535c838262a9229b400afe4d92c184 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 8 Oct 2013 21:26:34 +0200 Subject: winsys/radeon: add the implementation of fences from r300g --- src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 56 +++++++++++++++++++++++++++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 23 +++++++++++ 2 files changed, 79 insertions(+) (limited to 'src/gallium/winsys') diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index 0782e10c800..e5723a5874e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -65,6 +65,7 @@ #include "radeon_drm_cs.h" #include "util/u_memory.h" +#include "os/os_time.h" #include #include @@ -630,6 +631,58 @@ static boolean radeon_bo_is_referenced(struct radeon_winsys_cs *rcs, return FALSE; } +/* FENCES */ + +static struct pipe_fence_handle * +radeon_cs_create_fence(struct radeon_winsys_cs *rcs) +{ + struct radeon_drm_cs *cs = radeon_drm_cs(rcs); + struct pb_buffer *fence; + + /* Create a fence, which is a dummy BO. */ + fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1, TRUE, + RADEON_DOMAIN_GTT); + /* Add the fence as a dummy relocation. */ + cs->ws->base.cs_add_reloc(rcs, cs->ws->base.buffer_get_cs_handle(fence), + RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT); + return (struct pipe_fence_handle*)fence; +} + +static bool radeon_fence_wait(struct radeon_winsys *ws, + struct pipe_fence_handle *fence, + uint64_t timeout) +{ + struct pb_buffer *rfence = (struct pb_buffer*)fence; + + if (timeout == 0) + return !ws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE); + + if (timeout != PIPE_TIMEOUT_INFINITE) { + int64_t start_time = os_time_get(); + + /* Convert to microseconds. */ + timeout /= 1000; + + /* Wait in a loop. */ + while (ws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) { + if (os_time_get() - start_time >= timeout) { + return FALSE; + } + os_time_sleep(10); + } + return TRUE; + } + + ws->buffer_wait(rfence, RADEON_USAGE_READWRITE); + return TRUE; +} + +static void radeon_fence_reference(struct pipe_fence_handle **dst, + struct pipe_fence_handle *src) +{ + pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src); +} + void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws) { ws->base.cs_create = radeon_drm_cs_create; @@ -642,4 +695,7 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws) ws->base.cs_set_flush_callback = radeon_drm_cs_set_flush; ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced; ws->base.cs_sync_flush = radeon_drm_cs_sync_flush; + ws->base.cs_create_fence = radeon_cs_create_fence; + ws->base.fence_wait = radeon_fence_wait; + ws->base.fence_reference = radeon_fence_reference; } diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index 581cd841cd8..c0003711bee 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -484,6 +484,29 @@ struct radeon_winsys { */ void (*cs_sync_flush)(struct radeon_winsys_cs *cs); + /** + * Return a fence associated with the CS. The fence will be signalled + * once the CS is flushed and all commands in the CS are completed + * by the GPU. + */ + struct pipe_fence_handle *(*cs_create_fence)(struct radeon_winsys_cs *cs); + + /** + * Wait for the fence and return true if the fence has been signalled. + * The timeout of 0 will only return the status. + * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence + * is signalled. + */ + bool (*fence_wait)(struct radeon_winsys *ws, + struct pipe_fence_handle *fence, + uint64_t timeout); + + /** + * Reference counting for fences. + */ + void (*fence_reference)(struct pipe_fence_handle **dst, + struct pipe_fence_handle *src); + /** * Initialize surface * -- cgit v1.2.3