From 0e229b8c5aa5eb758cbc9e1176001e0f4d985a6a Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 6 Aug 2014 03:18:06 +0200 Subject: radeonsi: always prefer SWITCH_ON_EOP(0) on CIK The code is rewritten to take known constraints into account, while always using 0 by default. This should improve performance for multi-SE parts in theory. A debug option is also added for easier debugging. (If there are hangs, use the option. If the hangs go away, you have found the problem.) Reviewed-by: Alex Deucher v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver --- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/gallium/winsys/radeon') diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 910d06b5dba..21567bbcf01 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -392,6 +392,26 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL, &ws->info.max_se); + if (!ws->info.max_se) { + switch (ws->info.family) { + default: + ws->info.max_se = 1; + break; + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + case CHIP_BARTS: + case CHIP_CAYMAN: + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_BONAIRE: + ws->info.max_se = 2; + break; + case CHIP_HAWAII: + ws->info.max_se = 4; + break; + } + } + radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL, &ws->info.max_sh_per_se); -- cgit v1.2.3