From 6011d7cf2528a02f1737b25bc180c2076a076173 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 24 Feb 2016 00:58:38 +0100 Subject: gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tiling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags in IBs. Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle --- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/gallium/winsys/radeon/drm/radeon_drm_bo.c') diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index ce91af4486f..cd769f7ade9 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -671,21 +671,13 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf, } static void radeon_bo_set_tiling(struct pb_buffer *_buf, - struct radeon_winsys_cs *rcs, struct radeon_bo_metadata *md) { struct radeon_bo *bo = radeon_bo(_buf); - struct radeon_drm_cs *cs = radeon_drm_cs(rcs); struct drm_radeon_gem_set_tiling args; memset(&args, 0, sizeof(args)); - /* Tiling determines how DRM treats the buffer data. - * We must flush CS when changing it if the buffer is referenced. */ - if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) { - cs->flush_cs(cs->flush_data, 0, NULL); - } - os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE); if (md->microtile == RADEON_LAYOUT_TILED) -- cgit v1.2.3