From b8fb1d75ce95fe5d404b301ab31ca0c323967d14 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 10 May 2010 03:27:58 +0200
Subject: r600g: adapt to latest interfaces changes

- Wrapped the buffer and texture create/destroy/transfer/... functions
  using u_resource, which is then used to implement the resource functions.
- Implemented texture transfers.
  I left the buffer and texture transfers separate because one day we'll
  need a special codepath for textures.
- Added index_bias to the draw_*elements functions.
- Removed nonexistent *REP and *FOR instructions.
- Some pipe formats have changed channel ordering, so I've removed/fixed
  nonexistent ones.
- Added stubs for create/set/destroy sampler views.
- Added a naive implementation of vertex elements state (new CSO).
- Reworked {texture,buffer}_{from,to}_handle.
- Reorganized winsys files, removed dri,egl,python directories.
- Added a new build target dri-r600.
---
 src/gallium/winsys/r600/drm/r600d.h | 2122 +++++++++++++++++++++++++++++++++++
 1 file changed, 2122 insertions(+)
 create mode 100644 src/gallium/winsys/r600/drm/r600d.h

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
new file mode 100644
index 00000000000..5d13378627e
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -0,0 +1,2122 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600D_H
+#define R600D_H
+
+#define R600_CONFIG_REG_OFFSET                 0X00008000
+#define R600_CONFIG_REG_END                    0X0000AC00
+#define R600_CONTEXT_REG_OFFSET                0X00028000
+#define R600_CONTEXT_REG_END                   0X00029000
+#define R600_ALU_CONST_OFFSET                  0X00030000
+#define R600_ALU_CONST_END                     0X00032000
+#define R600_RESOURCE_OFFSET                   0X00038000
+#define R600_RESOURCE_END                      0X0003C000
+#define R600_SAMPLER_OFFSET                    0X0003C000
+#define R600_SAMPLER_END                       0X0003CFF0
+#define R600_CTL_CONST_OFFSET                  0X0003CFF0
+#define R600_CTL_CONST_END                     0X0003E200
+#define R600_LOOP_CONST_OFFSET                 0X0003E200
+#define R600_LOOP_CONST_END                    0X0003E380
+#define R600_BOOL_CONST_OFFSET                 0X0003E380
+#define R600_BOOL_CONST_END                    0X00040000
+
+#define PKT3_NOP                               0x10
+#define PKT3_INDIRECT_BUFFER_END               0x17
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_REG_RMW                           0x21
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_START_3D_CMDBUF                   0x24
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_DRAW_INDEX_IMMD_BE                0x29
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX                        0x2B
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_INDIRECT_BUFFER_MP                0x38
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define PKT3_MEM_WRITE                         0x3D
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_CP_INTERRUPT                      0x40
+#define PKT3_SURFACE_SYNC                      0x43
+#define PKT3_ME_INITIALIZE                     0x44
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_ONE_REG_WRITE                     0x57
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_ALU_CONST                     0x6A
+#define PKT3_SET_BOOL_CONST                    0x6B
+#define PKT3_SET_LOOP_CONST                    0x6C
+#define PKT3_SET_RESOURCE                      0x6D
+#define PKT3_SET_SAMPLER                       0x6E
+#define PKT3_SET_CTL_CONST                     0x6F
+#define PKT3_SURFACE_BASE_UPDATE               0x73
+
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
+
+/* Registers */
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_0280A0_ENDIAN                              0xFFFFFFFC
+#define   S_0280A0_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_0280A0_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_0280A0_FORMAT                              0xFFFFFF03
+#define     V_0280A0_COLOR_INVALID                     0x00000000
+#define     V_0280A0_COLOR_8                           0x00000001
+#define     V_0280A0_COLOR_4_4                         0x00000002
+#define     V_0280A0_COLOR_3_3_2                       0x00000003
+#define     V_0280A0_COLOR_16                          0x00000005
+#define     V_0280A0_COLOR_16_FLOAT                    0x00000006
+#define     V_0280A0_COLOR_8_8                         0x00000007
+#define     V_0280A0_COLOR_5_6_5                       0x00000008
+#define     V_0280A0_COLOR_6_5_5                       0x00000009
+#define     V_0280A0_COLOR_1_5_5_5                     0x0000000A
+#define     V_0280A0_COLOR_4_4_4_4                     0x0000000B
+#define     V_0280A0_COLOR_5_5_5_1                     0x0000000C
+#define     V_0280A0_COLOR_32                          0x0000000D
+#define     V_0280A0_COLOR_32_FLOAT                    0x0000000E
+#define     V_0280A0_COLOR_16_16                       0x0000000F
+#define     V_0280A0_COLOR_16_16_FLOAT                 0x00000010
+#define     V_0280A0_COLOR_8_24                        0x00000011
+#define     V_0280A0_COLOR_8_24_FLOAT                  0x00000012
+#define     V_0280A0_COLOR_24_8                        0x00000013
+#define     V_0280A0_COLOR_24_8_FLOAT                  0x00000014
+#define     V_0280A0_COLOR_10_11_11                    0x00000015
+#define     V_0280A0_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_0280A0_COLOR_11_11_10                    0x00000017
+#define     V_0280A0_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_0280A0_COLOR_2_10_10_10                  0x00000019
+#define     V_0280A0_COLOR_8_8_8_8                     0x0000001A
+#define     V_0280A0_COLOR_10_10_10_2                  0x0000001B
+#define     V_0280A0_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_0280A0_COLOR_32_32                       0x0000001D
+#define     V_0280A0_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_0280A0_COLOR_16_16_16_16                 0x0000001F
+#define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_0280A0_COLOR_32_32_32_32                 0x00000022
+#define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
+#define     V_0280A0_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_0280A0_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_0280A0_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_0280A0_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
+#define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
+#define   C_0280A0_READ_SIZE                           0xFFFF7FFF
+#define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
+#define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
+#define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
+#define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
+#define   C_0280A0_TILE_MODE                           0xFFF3FFFF
+#define   S_0280A0_BLEND_CLAMP(x)                      (((x) & 0x1) << 20)
+#define   G_0280A0_BLEND_CLAMP(x)                      (((x) >> 20) & 0x1)
+#define   C_0280A0_BLEND_CLAMP                         0xFFEFFFFF
+#define   S_0280A0_CLEAR_COLOR(x)                      (((x) & 0x1) << 21)
+#define   G_0280A0_CLEAR_COLOR(x)                      (((x) >> 21) & 0x1)
+#define   C_0280A0_CLEAR_COLOR                         0xFFDFFFFF
+#define   S_0280A0_BLEND_BYPASS(x)                     (((x) & 0x1) << 22)
+#define   G_0280A0_BLEND_BYPASS(x)                     (((x) >> 22) & 0x1)
+#define   C_0280A0_BLEND_BYPASS                        0xFFBFFFFF
+#define   S_0280A0_BLEND_FLOAT32(x)                    (((x) & 0x1) << 23)
+#define   G_0280A0_BLEND_FLOAT32(x)                    (((x) >> 23) & 0x1)
+#define   C_0280A0_BLEND_FLOAT32                       0xFF7FFFFF
+#define   S_0280A0_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 24)
+#define   G_0280A0_SIMPLE_FLOAT(x)                     (((x) >> 24) & 0x1)
+#define   C_0280A0_SIMPLE_FLOAT                        0xFEFFFFFF
+#define   S_0280A0_ROUND_MODE(x)                       (((x) & 0x1) << 25)
+#define   G_0280A0_ROUND_MODE(x)                       (((x) >> 25) & 0x1)
+#define   C_0280A0_ROUND_MODE                          0xFDFFFFFF
+#define   S_0280A0_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_0280A0_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_0280A0_TILE_COMPACT                        0xFBFFFFFF
+#define   S_0280A0_SOURCE_FORMAT(x)                    (((x) & 0x1) << 27)
+#define   G_0280A0_SOURCE_FORMAT(x)                    (((x) >> 27) & 0x1)
+#define   C_0280A0_SOURCE_FORMAT                       0xF7FFFFFF
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
+#define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
+#define   C_028010_FORMAT                              0xFFFFFFF8
+#define     V_028010_DEPTH_INVALID                     0x00000000
+#define     V_028010_DEPTH_16                          0x00000001
+#define     V_028010_DEPTH_X8_24                       0x00000002
+#define     V_028010_DEPTH_8_24                        0x00000003
+#define     V_028010_DEPTH_X8_24_FLOAT                 0x00000004
+#define     V_028010_DEPTH_8_24_FLOAT                  0x00000005
+#define     V_028010_DEPTH_32_FLOAT                    0x00000006
+#define     V_028010_DEPTH_X24_8_32_FLOAT              0x00000007
+#define   S_028010_READ_SIZE(x)                        (((x) & 0x1) << 3)
+#define   G_028010_READ_SIZE(x)                        (((x) >> 3) & 0x1)
+#define   C_028010_READ_SIZE                           0xFFFFFFF7
+#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)
+#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)
+#define   C_028010_ARRAY_MODE                          0xFFF87FFF
+#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)
+#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)
+#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF
+#define   S_028010_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_028010_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_028010_TILE_COMPACT                        0xFBFFFFFF
+#define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028000_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028000_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028000_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028000_SLICE_TILE_MAX                      0xC00003FF
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008DFC_SQ_CF_WORD0                         0x008DFC
+#define   S_008DFC_ADDR(x)                             (((x) & 0xFFFFFFFF) << 0)
+#define   G_008DFC_ADDR(x)                             (((x) >> 0) & 0xFFFFFFFF)
+#define   C_008DFC_ADDR                                0x00000000
+#define R_008DFC_SQ_CF_WORD1                         0x008DFC
+#define   S_008DFC_POP_COUNT(x)                        (((x) & 0x7) << 0)
+#define   G_008DFC_POP_COUNT(x)                        (((x) >> 0) & 0x7)
+#define   C_008DFC_POP_COUNT                           0xFFFFFFF8
+#define   S_008DFC_CF_CONST(x)                         (((x) & 0x1F) << 3)
+#define   G_008DFC_CF_CONST(x)                         (((x) >> 3) & 0x1F)
+#define   C_008DFC_CF_CONST                            0xFFFFFF07
+#define   S_008DFC_COND(x)                             (((x) & 0x3) << 8)
+#define   G_008DFC_COND(x)                             (((x) >> 8) & 0x3)
+#define   C_008DFC_COND                                0xFFFFFCFF
+#define   S_008DFC_COUNT(x)                            (((x) & 0x7) << 10)
+#define   G_008DFC_COUNT(x)                            (((x) >> 10) & 0x7)
+#define   C_008DFC_COUNT                               0xFFFFE3FF
+#define   S_008DFC_CALL_COUNT(x)                       (((x) & 0x3F) << 13)
+#define   G_008DFC_CALL_COUNT(x)                       (((x) >> 13) & 0x3F)
+#define   C_008DFC_CALL_COUNT                          0xFFF81FFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_NOP                    0x00000000
+#define     V_008DFC_SQ_CF_INST_TEX                    0x00000001
+#define     V_008DFC_SQ_CF_INST_VTX                    0x00000002
+#define     V_008DFC_SQ_CF_INST_VTX_TC                 0x00000003
+#define     V_008DFC_SQ_CF_INST_LOOP_START             0x00000004
+#define     V_008DFC_SQ_CF_INST_LOOP_END               0x00000005
+#define     V_008DFC_SQ_CF_INST_LOOP_START_DX10        0x00000006
+#define     V_008DFC_SQ_CF_INST_LOOP_START_NO_AL       0x00000007
+#define     V_008DFC_SQ_CF_INST_LOOP_CONTINUE          0x00000008
+#define     V_008DFC_SQ_CF_INST_LOOP_BREAK             0x00000009
+#define     V_008DFC_SQ_CF_INST_JUMP                   0x0000000A
+#define     V_008DFC_SQ_CF_INST_PUSH                   0x0000000B
+#define     V_008DFC_SQ_CF_INST_PUSH_ELSE              0x0000000C
+#define     V_008DFC_SQ_CF_INST_ELSE                   0x0000000D
+#define     V_008DFC_SQ_CF_INST_POP                    0x0000000E
+#define     V_008DFC_SQ_CF_INST_POP_JUMP               0x0000000F
+#define     V_008DFC_SQ_CF_INST_POP_PUSH               0x00000010
+#define     V_008DFC_SQ_CF_INST_POP_PUSH_ELSE          0x00000011
+#define     V_008DFC_SQ_CF_INST_CALL                   0x00000012
+#define     V_008DFC_SQ_CF_INST_CALL_FS                0x00000013
+#define     V_008DFC_SQ_CF_INST_RETURN                 0x00000014
+#define     V_008DFC_SQ_CF_INST_EMIT_VERTEX            0x00000015
+#define     V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX        0x00000016
+#define     V_008DFC_SQ_CF_INST_CUT_VERTEX             0x00000017
+#define     V_008DFC_SQ_CF_INST_KILL                   0x00000018
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD0                     0x008DFC
+#define   S_008DFC_ALU_ADDR(x)                         (((x) & 0x3FFFFF) << 0)
+#define   G_008DFC_ALU_ADDR(x)                         (((x) >> 0) & 0x3FFFFF)
+#define   C_008DFC_ALU_ADDR                            0xFFC00000
+#define   S_008DFC_KCACHE_BANK0(x)                     (((x) & 0xF) << 22)
+#define   G_008DFC_KCACHE_BANK0(x)                     (((x) >> 22) & 0xF)
+#define   C_008DFC_KCACHE_BANK0                        0xFC3FFFFF
+#define   S_008DFC_KCACHE_BANK1(x)                     (((x) & 0xF) << 26)
+#define   G_008DFC_KCACHE_BANK1(x)                     (((x) >> 26) & 0xF)
+#define   C_008DFC_KCACHE_BANK1                        0xC3FFFFFF
+#define   S_008DFC_KCACHE_MODE0(x)                     (((x) & 0x3) << 30)
+#define   G_008DFC_KCACHE_MODE0(x)                     (((x) >> 30) & 0x3)
+#define   C_008DFC_KCACHE_MODE0                        0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD1                     0x008DFC
+#define   S_008DFC_KCACHE_MODE1(x)                     (((x) & 0x3) << 0)
+#define   G_008DFC_KCACHE_MODE1(x)                     (((x) >> 0) & 0x3)
+#define   C_008DFC_KCACHE_MODE1                        0xFFFFFFFC
+#define   S_008DFC_KCACHE_ADDR0(x)                     (((x) & 0xFF) << 2)
+#define   G_008DFC_KCACHE_ADDR0(x)                     (((x) >> 2) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR0                        0xFFFFFC03
+#define   S_008DFC_KCACHE_ADDR1(x)                     (((x) & 0xFF) << 10)
+#define   G_008DFC_KCACHE_ADDR1(x)                     (((x) >> 10) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR1                        0xFFFC03FF
+#define   S_008DFC_ALU_COUNT(x)                        (((x) & 0x7F) << 18)
+#define   G_008DFC_ALU_COUNT(x)                        (((x) >> 18) & 0x7F)
+#define   C_008DFC_ALU_COUNT                           0xFE03FFFF
+#define   S_008DFC_USES_WATERFALL(x)                   (((x) & 0x1) << 25)
+#define   G_008DFC_USES_WATERFALL(x)                   (((x) >> 25) & 0x1)
+#define   C_008DFC_USES_WATERFALL                      0xFDFFFFFF
+#define   S_008DFC_CF_ALU_INST(x)                      (((x) & 0xF) << 26)
+#define   G_008DFC_CF_ALU_INST(x)                      (((x) >> 26) & 0xF)
+#define   C_008DFC_CF_ALU_INST                         0xC3FFFFFF
+#define     V_008DFC_SQ_CF_INST_ALU                    0x00000008
+#define     V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE        0x00000009
+#define     V_008DFC_SQ_CF_INST_ALU_POP_AFTER          0x0000000A
+#define     V_008DFC_SQ_CF_INST_ALU_POP2_AFTER         0x0000000B
+#define     V_008DFC_SQ_CF_INST_ALU_CONTINUE           0x0000000D
+#define     V_008DFC_SQ_CF_INST_ALU_BREAK              0x0000000E
+#define     V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER         0x0000000F
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0            0x008DFC
+#define   S_008DFC_ARRAY_BASE(x)                       (((x) & 0x1FFF) << 0)
+#define   G_008DFC_ARRAY_BASE(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_008DFC_ARRAY_BASE                          0xFFFFE000
+#define   S_008DFC_TYPE(x)                             (((x) & 0x3) << 13)
+#define   G_008DFC_TYPE(x)                             (((x) >> 13) & 0x3)
+#define   C_008DFC_TYPE                                0xFFFF9FFF
+#define   S_008DFC_RW_GPR(x)                           (((x) & 0x7F) << 15)
+#define   G_008DFC_RW_GPR(x)                           (((x) >> 15) & 0x7F)
+#define   C_008DFC_RW_GPR                              0xFFC07FFF
+#define   S_008DFC_RW_REL(x)                           (((x) & 0x1) << 22)
+#define   G_008DFC_RW_REL(x)                           (((x) >> 22) & 0x1)
+#define   C_008DFC_RW_REL                              0xFFBFFFFF
+#define   S_008DFC_INDEX_GPR(x)                        (((x) & 0x7F) << 23)
+#define   G_008DFC_INDEX_GPR(x)                        (((x) >> 23) & 0x7F)
+#define   C_008DFC_INDEX_GPR                           0xC07FFFFF
+#define   S_008DFC_ELEM_SIZE(x)                        (((x) & 0x3) << 30)
+#define   G_008DFC_ELEM_SIZE(x)                        (((x) >> 30) & 0x3)
+#define   C_008DFC_ELEM_SIZE                           0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1            0x008DFC
+#define   S_008DFC_BURST_COUNT(x)                      (((x) & 0xF) << 17)
+#define   G_008DFC_BURST_COUNT(x)                      (((x) >> 17) & 0xF)
+#define   C_008DFC_BURST_COUNT                         0xFFE1FFFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM0            0x00000020
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM1            0x00000021
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM2            0x00000022
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM3            0x00000023
+#define     V_008DFC_SQ_CF_INST_MEM_SCRATCH            0x00000024
+#define     V_008DFC_SQ_CF_INST_MEM_REDUCTION          0x00000025
+#define     V_008DFC_SQ_CF_INST_MEM_RING               0x00000026
+#define     V_008DFC_SQ_CF_INST_EXPORT                 0x00000027
+#define     V_008DFC_SQ_CF_INST_EXPORT_DONE            0x00000028
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF        0x008DFC
+#define   S_008DFC_ARRAY_SIZE(x)                       (((x) & 0xFFF) << 0)
+#define   G_008DFC_ARRAY_SIZE(x)                       (((x) >> 0) & 0xFFF)
+#define   C_008DFC_ARRAY_SIZE                          0xFFFFF000
+#define   S_008DFC_COMP_MASK(x)                        (((x) & 0xF) << 12)
+#define   G_008DFC_COMP_MASK(x)                        (((x) >> 12) & 0xF)
+#define   C_008DFC_COMP_MASK                           0xFFFF0FFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ       0x008DFC
+#define   S_008DFC_SEL_X(x)                            (((x) & 0x7) << 0)
+#define   G_008DFC_SEL_X(x)                            (((x) >> 0) & 0x7)
+#define   C_008DFC_SEL_X                               0xFFFFFFF8
+#define   S_008DFC_SEL_Y(x)                            (((x) & 0x7) << 3)
+#define   G_008DFC_SEL_Y(x)                            (((x) >> 3) & 0x7)
+#define   C_008DFC_SEL_Y                               0xFFFFFFC7
+#define   S_008DFC_SEL_Z(x)                            (((x) & 0x7) << 6)
+#define   G_008DFC_SEL_Z(x)                            (((x) >> 6) & 0x7)
+#define   C_008DFC_SEL_Z                               0xFFFFFE3F
+#define   S_008DFC_SEL_W(x)                            (((x) & 0x7) << 9)
+#define   G_008DFC_SEL_W(x)                            (((x) >> 9) & 0x7)
+#define   C_008DFC_SEL_W                               0xFFFFF1FF
+#define R_008DFC_SQ_VTX_WORD0                        0x008DFC
+#define   S_008DFC_VTX_INST(x)                         (((x) & 0x1F) << 0)
+#define   G_008DFC_VTX_INST(x)                         (((x) >> 0) & 0x1F)
+#define   C_008DFC_VTX_INST                            0xFFFFFFE0
+#define   S_008DFC_FETCH_TYPE(x)                       (((x) & 0x3) << 5)
+#define   G_008DFC_FETCH_TYPE(x)                       (((x) >> 5) & 0x3)
+#define   C_008DFC_FETCH_TYPE                          0xFFFFFF9F
+#define   S_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) & 0x1) << 7)
+#define   G_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) >> 7) & 0x1)
+#define   C_008DFC_FETCH_WHOLE_QUAD                    0xFFFFFF7F
+#define   S_008DFC_BUFFER_ID(x)                        (((x) & 0xFF) << 8)
+#define   G_008DFC_BUFFER_ID(x)                        (((x) >> 8) & 0xFF)
+#define   C_008DFC_BUFFER_ID                           0xFFFF00FF
+#define   S_008DFC_SRC_GPR(x)                          (((x) & 0x7F) << 16)
+#define   G_008DFC_SRC_GPR(x)                          (((x) >> 16) & 0x7F)
+#define   C_008DFC_SRC_GPR                             0xFF80FFFF
+#define   S_008DFC_SRC_REL(x)                          (((x) & 0x1) << 23)
+#define   G_008DFC_SRC_REL(x)                          (((x) >> 23) & 0x1)
+#define   C_008DFC_SRC_REL                             0xFF7FFFFF
+#define   S_008DFC_SRC_SEL_X(x)                        (((x) & 0x3) << 24)
+#define   G_008DFC_SRC_SEL_X(x)                        (((x) >> 24) & 0x3)
+#define   C_008DFC_SRC_SEL_X                           0xFCFFFFFF
+#define   S_008DFC_MEGA_FETCH_COUNT(x)                 (((x) & 0x3F) << 26)
+#define   G_008DFC_MEGA_FETCH_COUNT(x)                 (((x) >> 26) & 0x3F)
+#define   C_008DFC_MEGA_FETCH_COUNT                    0x03FFFFFF
+#define R_008DFC_SQ_VTX_WORD1                        0x008DFC
+#define   S_008DFC_DST_SEL_X(x)                        (((x) & 0x7) << 9)
+#define   G_008DFC_DST_SEL_X(x)                        (((x) >> 9) & 0x7)
+#define   C_008DFC_DST_SEL_X                           0xFFFFF1FF
+#define   S_008DFC_DST_SEL_Y(x)                        (((x) & 0x7) << 12)
+#define   G_008DFC_DST_SEL_Y(x)                        (((x) >> 12) & 0x7)
+#define   C_008DFC_DST_SEL_Y                           0xFFFF8FFF
+#define   S_008DFC_DST_SEL_Z(x)                        (((x) & 0x7) << 15)
+#define   G_008DFC_DST_SEL_Z(x)                        (((x) >> 15) & 0x7)
+#define   C_008DFC_DST_SEL_Z                           0xFFFC7FFF
+#define   S_008DFC_DST_SEL_W(x)                        (((x) & 0x7) << 18)
+#define   G_008DFC_DST_SEL_W(x)                        (((x) >> 18) & 0x7)
+#define   C_008DFC_DST_SEL_W                           0xFFE3FFFF
+#define   S_008DFC_USE_CONST_FIELDS(x)                 (((x) & 0x1) << 21)
+#define   G_008DFC_USE_CONST_FIELDS(x)                 (((x) >> 21) & 0x1)
+#define   C_008DFC_USE_CONST_FIELDS                    0xFFDFFFFF
+#define   S_008DFC_DATA_FORMAT(x)                      (((x) & 0x3F) << 22)
+#define   G_008DFC_DATA_FORMAT(x)                      (((x) >> 22) & 0x3F)
+#define   C_008DFC_DATA_FORMAT                         0xF03FFFFF
+#define   S_008DFC_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 28)
+#define   G_008DFC_NUM_FORMAT_ALL(x)                   (((x) >> 28) & 0x3)
+#define   C_008DFC_NUM_FORMAT_ALL                      0xCFFFFFFF
+#define   S_008DFC_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_FORMAT_COMP_ALL(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_FORMAT_COMP_ALL                     0xBFFFFFFF
+#define   S_008DFC_SRF_MODE_ALL(x)                     (((x) & 0x1) << 31)
+#define   G_008DFC_SRF_MODE_ALL(x)                     (((x) >> 31) & 0x1)
+#define   C_008DFC_SRF_MODE_ALL                        0x7FFFFFFF
+#define R_008DFC_SQ_VTX_WORD1_GPR                    0x008DFC
+#define   S_008DFC_DST_GPR(x)                          (((x) & 0x7F) << 0)
+#define   G_008DFC_DST_GPR(x)                          (((x) >> 0) & 0x7F)
+#define   C_008DFC_DST_GPR                             0xFFFFFF80
+#define   S_008DFC_DST_REL(x)                          (((x) & 0x1) << 7)
+#define   G_008DFC_DST_REL(x)                          (((x) >> 7) & 0x1)
+#define   C_008DFC_DST_REL                             0xFFFFFF7F
+#define R_008DFC_SQ_VTX_WORD2                        0x008DFC
+#define   S_008DFC_OFFSET(x)                           (((x) & 0xFFFF) << 0)
+#define   G_008DFC_OFFSET(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_OFFSET                              0xFFFF0000
+#define   S_008DFC_ENDIAN_SWAP(x)                      (((x) & 0x3) << 16)
+#define   G_008DFC_ENDIAN_SWAP(x)                      (((x) >> 16) & 0x3)
+#define   C_008DFC_ENDIAN_SWAP                         0xFFFCFFFF
+#define   S_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) & 0x1) << 18)
+#define   G_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) >> 18) & 0x1)
+#define   C_008DFC_CONST_BUF_NO_STRIDE                 0xFFFBFFFF
+#define   S_008DFC_MEGA_FETCH(x)                       (((x) & 0x1) << 19)
+#define   G_008DFC_MEGA_FETCH(x)                       (((x) >> 19) & 0x1)
+#define   C_008DFC_MEGA_FETCH                          0xFFF7FFFF
+#define   S_008DFC_ALT_CONST(x)                        (((x) & 0x1) << 20)
+#define   G_008DFC_ALT_CONST(x)                        (((x) >> 20) & 0x1)
+#define   C_008DFC_ALT_CONST                           0xFFEFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PARAM_GEN_ADDR(x)                   (((x) & 0x7F) << 19)
+#define   G_0286CC_PARAM_GEN_ADDR(x)                   (((x) >> 19) & 0x7F)
+#define   C_0286CC_PARAM_GEN_ADDR                      0xFC07FFFF
+#define   S_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) & 0x3) << 26)
+#define   G_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) >> 26) & 0x3)
+#define   C_0286CC_BARYC_SAMPLE_CNTL                   0xF3FFFFFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define   S_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) & 0x1) << 31)
+#define   G_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) >> 31) & 0x1)
+#define   C_0286CC_BARYC_AT_SAMPLE_ENA                 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_GEN_INDEX_PIX(x)                    (((x) & 0x1) << 0)
+#define   G_0286D0_GEN_INDEX_PIX(x)                    (((x) >> 0) & 0x1)
+#define   C_0286D0_GEN_INDEX_PIX                       0xFFFFFFFE
+#define   S_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) & 0x7F) << 1)
+#define   G_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) >> 1) & 0x7F)
+#define   C_0286D0_GEN_INDEX_PIX_ADDR                  0xFFFFFF01
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
+#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
+#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
+#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
+#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
+#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
+#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
+#define R_02800C_DB_DEPTH_BASE                       0x02800C
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
+#define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
+#define R_028C48_PA_SC_AA_MASK                       0x028C48
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define R_028820_PA_CL_NANINF_CNTL                   0x028820
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x028C18
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x028440
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x028448
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x028450
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x028254
+#define R_028780_CB_BLEND0_CONTROL                   0x028780
+#define R_028784_CB_BLEND1_CONTROL                   0x028784
+#define R_028788_CB_BLEND2_CONTROL                   0x028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x02878C
+#define R_028790_CB_BLEND4_CONTROL                   0x028790
+#define R_028794_CB_BLEND5_CONTROL                   0x028794
+#define R_028798_CB_BLEND6_CONTROL                   0x028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x02879C
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define R_028028_DB_STENCIL_CLEAR                    0x028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x02802C
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define R_02880C_DB_SHADER_CONTROL                   0x02880C
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define R_028D2C_DB_SRESULTS_COMPARE_STATE1          0x028D2C
+#define R_028D30_DB_PRELOAD_CONTROL                  0x028D30
+#define R_028D44_DB_ALPHA_TO_MASK                    0x028D44
+#define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x0286C0
+#define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
+#define R_028854_SQ_PGM_EXPORTS_PS                   0x028854
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define R_028A7C_VGT_DMA_INDEX_TYPE                  0x028A7C
+#define R_028A88_VGT_DMA_NUM_INSTANCES               0x028A88
+#define R_008970_VGT_NUM_INDICES                     0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define R_028238_CB_TARGET_MASK                      0x028238
+#define R_02823C_CB_SHADER_MASK                      0x02823C
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028064_CB_COLOR1_SIZE                      0x028064
+#define R_028068_CB_COLOR2_SIZE                      0x028068
+#define R_02806C_CB_COLOR3_SIZE                      0x02806C
+#define R_028070_CB_COLOR4_SIZE                      0x028070
+#define R_028074_CB_COLOR5_SIZE                      0x028074
+#define R_028078_CB_COLOR6_SIZE                      0x028078
+#define R_02807C_CB_COLOR7_SIZE                      0x02807C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define R_028044_CB_COLOR1_BASE                      0x028044
+#define R_028048_CB_COLOR2_BASE                      0x028048
+#define R_02804C_CB_COLOR3_BASE                      0x02804C
+#define R_028050_CB_COLOR4_BASE                      0x028050
+#define R_028054_CB_COLOR5_BASE                      0x028054
+#define R_028058_CB_COLOR6_BASE                      0x028058
+#define R_02805C_CB_COLOR7_BASE                      0x02805C
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define   S_028C04_MSAA_NUM_SAMPLES(x)                 (((x) & 0x3) << 0)
+#define   G_028C04_MSAA_NUM_SAMPLES(x)                 (((x) >> 0) & 0x3)
+#define   C_028C04_MSAA_NUM_SAMPLES                    0xFFFFFFFC
+#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
+#define   G_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) >> 4) & 0x1)
+#define   C_028C04_AA_MASK_CENTROID_DTMN               0xFFFFFFEF
+#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xF) << 13)
+#define   G_028C04_MAX_SAMPLE_DIST(x)                  (((x) >> 13) & 0xF)
+#define   C_028C04_MAX_SAMPLE_DIST                     0xFFFE1FFF
+#define R_0288CC_SQ_PGM_CF_OFFSET_PS                 0x0288CC
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define R_0288D0_SQ_PGM_CF_OFFSET_VS                 0x0288D0
+#define R_028840_SQ_PGM_START_PS                     0x028840
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define R_028858_SQ_PGM_START_VS                     0x028858
+#define R_028080_CB_COLOR0_VIEW                      0x028080
+#define   S_028080_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028080_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028080_SLICE_START                         0xFFFFF800
+#define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028080_SLICE_MAX                           0xFF001FFF
+#define R_028100_CB_COLOR0_MASK                      0x028100
+#define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
+#define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
+#define   C_028100_CMASK_BLOCK_MAX                     0xFFFFF000
+#define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
+#define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
+#define   C_028100_FMASK_TILE_MAX                      0x00000FFF
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define   S_028040_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028040_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028040_BASE_256B                           0x00000000
+#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
+#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
+#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280C0_BASE_256B                           0x00000000
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028614_SPI_VS_OUT_ID_0                     0x028614
+#define   S_028614_SEMANTIC_0(x)                       (((x) & 0xFF) << 0)
+#define   G_028614_SEMANTIC_0(x)                       (((x) >> 0) & 0xFF)
+#define   C_028614_SEMANTIC_0                          0xFFFFFF00
+#define   S_028614_SEMANTIC_1(x)                       (((x) & 0xFF) << 8)
+#define   G_028614_SEMANTIC_1(x)                       (((x) >> 8) & 0xFF)
+#define   C_028614_SEMANTIC_1                          0xFFFF00FF
+#define   S_028614_SEMANTIC_2(x)                       (((x) & 0xFF) << 16)
+#define   G_028614_SEMANTIC_2(x)                       (((x) >> 16) & 0xFF)
+#define   C_028614_SEMANTIC_2                          0xFF00FFFF
+#define   S_028614_SEMANTIC_3(x)                       (((x) & 0xFF) << 24)
+#define   G_028614_SEMANTIC_3(x)                       (((x) >> 24) & 0xFF)
+#define   C_028614_SEMANTIC_3                          0x00FFFFFF
+#define R_028618_SPI_VS_OUT_ID_1                     0x028618
+#define R_02861C_SPI_VS_OUT_ID_2                     0x02861C
+#define R_028620_SPI_VS_OUT_ID_3                     0x028620
+#define R_028624_SPI_VS_OUT_ID_4                     0x028624
+#define R_028628_SPI_VS_OUT_ID_5                     0x028628
+#define R_02862C_SPI_VS_OUT_ID_6                     0x02862C
+#define R_028630_SPI_VS_OUT_ID_7                     0x028630
+#define R_028634_SPI_VS_OUT_ID_8                     0x028634
+#define R_028638_SPI_VS_OUT_ID_9                     0x028638
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define     V_038004_COLOR_INVALID                     0x00000000
+#define     V_038004_COLOR_8                           0x00000001
+#define     V_038004_COLOR_4_4                         0x00000002
+#define     V_038004_COLOR_3_3_2                       0x00000003
+#define     V_038004_COLOR_16                          0x00000005
+#define     V_038004_COLOR_16_FLOAT                    0x00000006
+#define     V_038004_COLOR_8_8                         0x00000007
+#define     V_038004_COLOR_5_6_5                       0x00000008
+#define     V_038004_COLOR_6_5_5                       0x00000009
+#define     V_038004_COLOR_1_5_5_5                     0x0000000A
+#define     V_038004_COLOR_4_4_4_4                     0x0000000B
+#define     V_038004_COLOR_5_5_5_1                     0x0000000C
+#define     V_038004_COLOR_32                          0x0000000D
+#define     V_038004_COLOR_32_FLOAT                    0x0000000E
+#define     V_038004_COLOR_16_16                       0x0000000F
+#define     V_038004_COLOR_16_16_FLOAT                 0x00000010
+#define     V_038004_COLOR_8_24                        0x00000011
+#define     V_038004_COLOR_8_24_FLOAT                  0x00000012
+#define     V_038004_COLOR_24_8                        0x00000013
+#define     V_038004_COLOR_24_8_FLOAT                  0x00000014
+#define     V_038004_COLOR_10_11_11                    0x00000015
+#define     V_038004_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_038004_COLOR_11_11_10                    0x00000017
+#define     V_038004_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_038004_COLOR_2_10_10_10                  0x00000019
+#define     V_038004_COLOR_8_8_8_8                     0x0000001A
+#define     V_038004_COLOR_10_10_10_2                  0x0000001B
+#define     V_038004_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_038004_COLOR_32_32                       0x0000001D
+#define     V_038004_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_038004_COLOR_16_16_16_16                 0x0000001F
+#define     V_038004_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_038004_COLOR_32_32_32_32                 0x00000022
+#define     V_038004_COLOR_32_32_32_32_FLOAT           0x00000023
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define R_008C00_SQ_CONFIG                           0x008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE                           0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C                        0xFFFFFFFD
+#define   S_008C00_DX9_CONSTS(x)                       (((x) & 0x1) << 2)
+#define   G_008C00_DX9_CONSTS(x)                       (((x) >> 2) & 0x1)
+#define   C_008C00_DX9_CONSTS                          0xFFFFFFFB
+#define   S_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) & 0x1) << 3)
+#define   G_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) >> 3) & 0x1)
+#define   C_008C00_ALU_INST_PREFER_VECTOR              0xFFFFFFF7
+#define   S_008C00_DX10_CLAMP(x)                       (((x) & 0x1) << 4)
+#define   G_008C00_DX10_CLAMP(x)                       (((x) >> 4) & 0x1)
+#define   C_008C00_DX10_CLAMP                          0xFFFFFFEF
+#define   S_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) & 0x1) << 5)
+#define   G_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) >> 5) & 0x1)
+#define   C_008C00_ALU_PREFER_ONE_WATERFALL            0xFFFFFFDF
+#define   S_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) & 0x1) << 6)
+#define   G_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) >> 6) & 0x1)
+#define   C_008C00_ALU_MAX_ONE_WATERFALL               0xFFFFFFBF
+#define   S_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) & 0x3) << 8)
+#define   G_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) >> 8) & 0x3)
+#define   C_008C00_CLAUSE_SEQ_PRIO                     0xFFFFFCFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO                             0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO                             0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO                             0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO                             0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS                         0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS                         0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS                0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS                         0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS                         0xFF00FFFF
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x008C0C
+#define   S_008C0C_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_PS_THREADS                      0xFFFFFF00
+#define   S_008C0C_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C0C_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C0C_NUM_VS_THREADS                      0xFFFF00FF
+#define   S_008C0C_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_GS_THREADS                      0xFF00FFFF
+#define   S_008C0C_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C0C_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C0C_NUM_ES_THREADS                      0x00FFFFFF
+#define R_008C10_SQ_STACK_RESOURCE_MGMT_1            0x008C10
+#define   S_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C10_NUM_PS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C10_NUM_VS_STACK_ENTRIES                0xF000FFFF
+#define R_008C14_SQ_STACK_RESOURCE_MGMT_2            0x008C14
+#define   S_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C14_NUM_GS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C14_NUM_ES_STACK_ENTRIES                0xF000FFFF
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x008D8C
+#define   S_008D8C_RING0_OFFSET(x)                     (((x) & 0xFF) << 0)
+#define   G_008D8C_RING0_OFFSET(x)                     (((x) >> 0) & 0xFF)
+#define   C_008D8C_RING0_OFFSET                        0xFFFFFF00
+#define   S_008D8C_ISOLATE_ES_ENABLE(x)                (((x) & 0x1) << 12)
+#define   G_008D8C_ISOLATE_ES_ENABLE(x)                (((x) >> 12) & 0x1)
+#define   C_008D8C_ISOLATE_ES_ENABLE                   0xFFFFEFFF
+#define   S_008D8C_ISOLATE_GS_ENABLE(x)                (((x) & 0x1) << 13)
+#define   G_008D8C_ISOLATE_GS_ENABLE(x)                (((x) >> 13) & 0x1)
+#define   C_008D8C_ISOLATE_GS_ENABLE                   0xFFFFDFFF
+#define   S_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) & 0x1) << 14)
+#define   G_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) >> 14) & 0x1)
+#define   C_008D8C_VS_PC_LIMIT_ENABLE                  0xFFFFBFFF
+#define R_009508_TA_CNTL_AUX                         0x009508
+#define   S_009508_DISABLE_CUBE_WRAP(x)                (((x) & 0x1) << 0)
+#define   G_009508_DISABLE_CUBE_WRAP(x)                (((x) >> 0) & 0x1)
+#define   C_009508_DISABLE_CUBE_WRAP                   0xFFFFFFFE
+#define   S_009508_SYNC_GRADIENT(x)                    (((x) & 0x1) << 24)
+#define   G_009508_SYNC_GRADIENT(x)                    (((x) >> 24) & 0x1)
+#define   C_009508_SYNC_GRADIENT                       0xFEFFFFFF
+#define   S_009508_SYNC_WALKER(x)                      (((x) & 0x1) << 25)
+#define   G_009508_SYNC_WALKER(x)                      (((x) >> 25) & 0x1)
+#define   C_009508_SYNC_WALKER                         0xFDFFFFFF
+#define   S_009508_SYNC_ALIGNER(x)                     (((x) & 0x1) << 26)
+#define   G_009508_SYNC_ALIGNER(x)                     (((x) >> 26) & 0x1)
+#define   C_009508_SYNC_ALIGNER                        0xFBFFFFFF
+#define   S_009508_BILINEAR_PRECISION(x)               (((x) & 0x1) << 31)
+#define   G_009508_BILINEAR_PRECISION(x)               (((x) >> 31) & 0x1)
+#define   C_009508_BILINEAR_PRECISION                  0x7FFFFFFF
+#define R_009714_VC_ENHANCE                          0x009714
+#define R_009830_DB_DEBUG                            0x009830
+#define R_009838_DB_WATERMARKS                       0x009838
+#define   S_009838_DEPTH_FREE(x)                       (((x) & 0x1F) << 0)
+#define   G_009838_DEPTH_FREE(x)                       (((x) >> 0) & 0x1F)
+#define   C_009838_DEPTH_FREE                          0xFFFFFFE0
+#define   S_009838_DEPTH_FLUSH(x)                      (((x) & 0x3F) << 5)
+#define   G_009838_DEPTH_FLUSH(x)                      (((x) >> 5) & 0x3F)
+#define   C_009838_DEPTH_FLUSH                         0xFFFFF81F
+#define   S_009838_FORCE_SUMMARIZE(x)                  (((x) & 0xF) << 11)
+#define   G_009838_FORCE_SUMMARIZE(x)                  (((x) >> 11) & 0xF)
+#define   C_009838_FORCE_SUMMARIZE                     0xFFFF87FF
+#define   S_009838_DEPTH_PENDING_FREE(x)               (((x) & 0x1F) << 15)
+#define   G_009838_DEPTH_PENDING_FREE(x)               (((x) >> 15) & 0x1F)
+#define   C_009838_DEPTH_PENDING_FREE                  0xFFF07FFF
+#define   S_009838_DEPTH_CACHELINE_FREE(x)             (((x) & 0x1F) << 20)
+#define   G_009838_DEPTH_CACHELINE_FREE(x)             (((x) >> 20) & 0x1F)
+#define   C_009838_DEPTH_CACHELINE_FREE                0xFE0FFFFF
+#define   S_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) & 0x1) << 25)
+#define   G_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) >> 25) & 0x1)
+#define   C_009838_EARLY_Z_PANIC_DISABLE               0xFDFFFFFF
+#define   S_009838_LATE_Z_PANIC_DISABLE(x)             (((x) & 0x1) << 26)
+#define   G_009838_LATE_Z_PANIC_DISABLE(x)             (((x) >> 26) & 0x1)
+#define   C_009838_LATE_Z_PANIC_DISABLE                0xFBFFFFFF
+#define   S_009838_RE_Z_PANIC_DISABLE(x)               (((x) & 0x1) << 27)
+#define   G_009838_RE_Z_PANIC_DISABLE(x)               (((x) >> 27) & 0x1)
+#define   C_009838_RE_Z_PANIC_DISABLE                  0xF7FFFFFF
+#define   S_009838_DB_EXTRA_DEBUG(x)                   (((x) & 0xF) << 28)
+#define   G_009838_DB_EXTRA_DEBUG(x)                   (((x) >> 28) & 0xF)
+#define   C_009838_DB_EXTRA_DEBUG                      0x0FFFFFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x028200
+#define   S_028200_WINDOW_X_OFFSET(x)                  (((x) & 0x7FFF) << 0)
+#define   G_028200_WINDOW_X_OFFSET(x)                  (((x) >> 0) & 0x7FFF)
+#define   C_028200_WINDOW_X_OFFSET                     0xFFFF8000
+#define   S_028200_WINDOW_Y_OFFSET(x)                  (((x) & 0x7FFF) << 16)
+#define   G_028200_WINDOW_Y_OFFSET(x)                  (((x) >> 16) & 0x7FFF)
+#define   C_028200_WINDOW_Y_OFFSET                     0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x02820C
+#define   S_02820C_CLIP_RULE(x)                        (((x) & 0xFFFF) << 0)
+#define   G_02820C_CLIP_RULE(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_02820C_CLIP_RULE                           0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x028210
+#define   S_028210_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028210_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028210_TL_X                                0xFFFFC000
+#define   S_028210_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028210_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028210_TL_Y                                0xC000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x028214
+#define   S_028214_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028214_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028214_BR_X                                0xFFFFC000
+#define   S_028214_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028214_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028214_BR_Y                                0xC000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x02822C
+#define R_028230_PA_SC_EDGERULE                      0x028230
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x0282D0
+#define   S_0282D0_VPORT_ZMIN(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D0_VPORT_ZMIN(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D0_VPORT_ZMIN                          0x00000000
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x0282D4
+#define   S_0282D4_VPORT_ZMAX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D4_VPORT_ZMAX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D4_VPORT_ZMAX                          0x00000000
+#define R_028350_SX_MISC                             0x028350
+#define   S_028350_MULTIPASS(x)                        (((x) & 0x1) << 0)
+#define   G_028350_MULTIPASS(x)                        (((x) >> 0) & 0x1)
+#define   C_028350_MULTIPASS                           0xFFFFFFFE
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x028380
+#define   S_028380_SEMANTIC_ID(x)                      (((x) & 0xFF) << 0)
+#define   G_028380_SEMANTIC_ID(x)                      (((x) >> 0) & 0xFF)
+#define   C_028380_SEMANTIC_ID                         0xFFFFFF00
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x02838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x02839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x0283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x0283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x0283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x0283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x0283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x0283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x0283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x0283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x0283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x0283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x0283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x0283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x0283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x0283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x0283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x0283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x0283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x0283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x0283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x0283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x0283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x0283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x0283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x0283FC
+#define R_028400_VGT_MAX_VTX_INDX                    0x028400
+#define   S_028400_MAX_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028400_MAX_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028400_MAX_INDX                            0x00000000
+#define R_028404_VGT_MIN_VTX_INDX                    0x028404
+#define   S_028404_MIN_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028404_MIN_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028404_MIN_INDX                            0x00000000
+#define R_028408_VGT_INDX_OFFSET                     0x028408
+#define   S_028408_INDX_OFFSET(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028408_INDX_OFFSET(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028408_INDX_OFFSET                         0x00000000
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x02840C
+#define   S_02840C_RESET_INDX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02840C_RESET_INDX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02840C_RESET_INDX                          0x00000000
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+#define R_028414_CB_BLEND_RED                        0x028414
+#define   S_028414_BLEND_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028414_BLEND_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028414_BLEND_RED                           0x00000000
+#define R_028418_CB_BLEND_GREEN                      0x028418
+#define   S_028418_BLEND_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028418_BLEND_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028418_BLEND_GREEN                         0x00000000
+#define R_02841C_CB_BLEND_BLUE                       0x02841C
+#define   S_02841C_BLEND_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02841C_BLEND_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02841C_BLEND_BLUE                          0x00000000
+#define R_028420_CB_BLEND_ALPHA                      0x028420
+#define   S_028420_BLEND_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028420_BLEND_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028420_BLEND_ALPHA                         0x00000000
+#define R_028438_SX_ALPHA_REF                        0x028438
+#define   S_028438_ALPHA_REF(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028438_ALPHA_REF(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028438_ALPHA_REF                           0x00000000
+#define R_0286C8_SPI_THREAD_GROUPING                 0x0286C8
+#define   S_0286C8_PS_GROUPING(x)                      (((x) & 0x1F) << 0)
+#define   G_0286C8_PS_GROUPING(x)                      (((x) >> 0) & 0x1F)
+#define   C_0286C8_PS_GROUPING                         0xFFFFFFE0
+#define   S_0286C8_VS_GROUPING(x)                      (((x) & 0x1F) << 8)
+#define   G_0286C8_VS_GROUPING(x)                      (((x) >> 8) & 0x1F)
+#define   C_0286C8_VS_GROUPING                         0xFFFFE0FF
+#define   S_0286C8_GS_GROUPING(x)                      (((x) & 0x1F) << 16)
+#define   G_0286C8_GS_GROUPING(x)                      (((x) >> 16) & 0x1F)
+#define   C_0286C8_GS_GROUPING                         0xFFE0FFFF
+#define   S_0286C8_ES_GROUPING(x)                      (((x) & 0x1F) << 24)
+#define   G_0286C8_ES_GROUPING(x)                      (((x) >> 24) & 0x1F)
+#define   C_0286C8_ES_GROUPING                         0xE0FFFFFF
+#define R_0286D8_SPI_INPUT_Z                         0x0286D8
+#define   S_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) & 0x1) << 0)
+#define   G_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) >> 0) & 0x1)
+#define   C_0286D8_PROVIDE_Z_TO_SPI                    0xFFFFFFFE
+#define R_0286DC_SPI_FOG_CNTL                        0x0286DC
+#define   S_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) & 0x1) << 0)
+#define   G_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) >> 0) & 0x1)
+#define   C_0286DC_PASS_FOG_THROUGH_PS                 0xFFFFFFFE
+#define   S_0286DC_PIXEL_FOG_FUNC(x)                   (((x) & 0x3) << 1)
+#define   G_0286DC_PIXEL_FOG_FUNC(x)                   (((x) >> 1) & 0x3)
+#define   C_0286DC_PIXEL_FOG_FUNC                      0xFFFFFFF9
+#define   S_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) & 0x1) << 3)
+#define   G_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) >> 3) & 0x1)
+#define   C_0286DC_PIXEL_FOG_SRC_SEL                   0xFFFFFFF7
+#define   S_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) & 0x1) << 4)
+#define   G_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) >> 4) & 0x1)
+#define   C_0286DC_VS_FOG_CLAMP_DISABLE                0xFFFFFFEF
+#define R_0286E0_SPI_FOG_FUNC_SCALE                  0x0286E0
+#define   S_0286E0_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E0_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E0_VALUE                               0x00000000
+#define R_0286E4_SPI_FOG_FUNC_BIAS                   0x0286E4
+#define   S_0286E4_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E4_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E4_VALUE                               0x00000000
+#define R_0287A0_CB_SHADER_CONTROL                   0x0287A0
+#define   S_0287A0_RT0_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_0287A0_RT0_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_0287A0_RT0_ENABLE                          0xFFFFFFFE
+#define   S_0287A0_RT1_ENABLE(x)                       (((x) & 0x1) << 1)
+#define   G_0287A0_RT1_ENABLE(x)                       (((x) >> 1) & 0x1)
+#define   C_0287A0_RT1_ENABLE                          0xFFFFFFFD
+#define   S_0287A0_RT2_ENABLE(x)                       (((x) & 0x1) << 2)
+#define   G_0287A0_RT2_ENABLE(x)                       (((x) >> 2) & 0x1)
+#define   C_0287A0_RT2_ENABLE                          0xFFFFFFFB
+#define   S_0287A0_RT3_ENABLE(x)                       (((x) & 0x1) << 3)
+#define   G_0287A0_RT3_ENABLE(x)                       (((x) >> 3) & 0x1)
+#define   C_0287A0_RT3_ENABLE                          0xFFFFFFF7
+#define   S_0287A0_RT4_ENABLE(x)                       (((x) & 0x1) << 4)
+#define   G_0287A0_RT4_ENABLE(x)                       (((x) >> 4) & 0x1)
+#define   C_0287A0_RT4_ENABLE                          0xFFFFFFEF
+#define   S_0287A0_RT5_ENABLE(x)                       (((x) & 0x1) << 5)
+#define   G_0287A0_RT5_ENABLE(x)                       (((x) >> 5) & 0x1)
+#define   C_0287A0_RT5_ENABLE                          0xFFFFFFDF
+#define   S_0287A0_RT6_ENABLE(x)                       (((x) & 0x1) << 6)
+#define   G_0287A0_RT6_ENABLE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287A0_RT6_ENABLE                          0xFFFFFFBF
+#define   S_0287A0_RT7_ENABLE(x)                       (((x) & 0x1) << 7)
+#define   G_0287A0_RT7_ENABLE(x)                       (((x) >> 7) & 0x1)
+#define   C_0287A0_RT7_ENABLE                          0xFFFFFF7F
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define   S_028894_PGM_START(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028894_PGM_START(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028894_PGM_START                           0x00000000
+#define R_0288A4_SQ_PGM_RESOURCES_FS                 0x0288A4
+#define   S_0288A4_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_0288A4_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_0288A4_NUM_GPRS                            0xFFFFFF00
+#define   S_0288A4_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_0288A4_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_0288A4_STACK_SIZE                          0xFFFF00FF
+#define   S_0288A4_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_0288A4_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_0288A4_DX10_CLAMP                          0xFFDFFFFF
+#define R_0288A8_SQ_ESGS_RING_ITEMSIZE               0x0288A8
+#define   S_0288A8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288A8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288A8_ITEMSIZE                            0xFFFF8000
+#define R_0288AC_SQ_GSVS_RING_ITEMSIZE               0x0288AC
+#define   S_0288AC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288AC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288AC_ITEMSIZE                            0xFFFF8000
+#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE              0x0288B0
+#define   S_0288B0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B0_ITEMSIZE                            0xFFFF8000
+#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE              0x0288B4
+#define   S_0288B4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B4_ITEMSIZE                            0xFFFF8000
+#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE              0x0288B8
+#define   S_0288B8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B8_ITEMSIZE                            0xFFFF8000
+#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE              0x0288BC
+#define   S_0288BC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288BC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288BC_ITEMSIZE                            0xFFFF8000
+#define R_0288C0_SQ_FBUF_RING_ITEMSIZE               0x0288C0
+#define   S_0288C0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C0_ITEMSIZE                            0xFFFF8000
+#define R_0288C4_SQ_REDUC_RING_ITEMSIZE              0x0288C4
+#define   S_0288C4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C4_ITEMSIZE                            0xFFFF8000
+#define R_0288C8_SQ_GS_VERT_ITEMSIZE                 0x0288C8
+#define   S_0288C8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C8_ITEMSIZE                            0xFFFF8000
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define   S_0288DC_PGM_CF_OFFSET(x)                    (((x) & 0xFFFFF) << 0)
+#define   G_0288DC_PGM_CF_OFFSET(x)                    (((x) >> 0) & 0xFFFFF)
+#define   C_0288DC_PGM_CF_OFFSET                       0xFFF00000
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x028A10
+#define   S_028A10_PATH_SELECT(x)                      (((x) & 0x3) << 0)
+#define   G_028A10_PATH_SELECT(x)                      (((x) >> 0) & 0x3)
+#define   C_028A10_PATH_SELECT                         0xFFFFFFFC
+#define R_028A14_VGT_HOS_CNTL                        0x028A14
+#define   S_028A14_TESS_MODE(x)                        (((x) & 0x3) << 0)
+#define   G_028A14_TESS_MODE(x)                        (((x) >> 0) & 0x3)
+#define   C_028A14_TESS_MODE                           0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x028A18
+#define   S_028A18_MAX_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A18_MAX_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A18_MAX_TESS                            0x00000000
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x028A1C
+#define   S_028A1C_MIN_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A1C_MIN_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A1C_MIN_TESS                            0x00000000
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x028A20
+#define   S_028A20_REUSE_DEPTH(x)                      (((x) & 0xFF) << 0)
+#define   G_028A20_REUSE_DEPTH(x)                      (((x) >> 0) & 0xFF)
+#define   C_028A20_REUSE_DEPTH                         0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x028A24
+#define   S_028A24_PRIM_TYPE(x)                        (((x) & 0x1F) << 0)
+#define   G_028A24_PRIM_TYPE(x)                        (((x) >> 0) & 0x1F)
+#define   C_028A24_PRIM_TYPE                           0xFFFFFFE0
+#define   S_028A24_RETAIN_ORDER(x)                     (((x) & 0x1) << 14)
+#define   G_028A24_RETAIN_ORDER(x)                     (((x) >> 14) & 0x1)
+#define   C_028A24_RETAIN_ORDER                        0xFFFFBFFF
+#define   S_028A24_RETAIN_QUADS(x)                     (((x) & 0x1) << 15)
+#define   G_028A24_RETAIN_QUADS(x)                     (((x) >> 15) & 0x1)
+#define   C_028A24_RETAIN_QUADS                        0xFFFF7FFF
+#define   S_028A24_PRIM_ORDER(x)                       (((x) & 0x7) << 16)
+#define   G_028A24_PRIM_ORDER(x)                       (((x) >> 16) & 0x7)
+#define   C_028A24_PRIM_ORDER                          0xFFF8FFFF
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x028A28
+#define   S_028A28_FIRST_DECR(x)                       (((x) & 0xF) << 0)
+#define   G_028A28_FIRST_DECR(x)                       (((x) >> 0) & 0xF)
+#define   C_028A28_FIRST_DECR                          0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR                      0x028A2C
+#define   S_028A2C_DECR(x)                             (((x) & 0xF) << 0)
+#define   G_028A2C_DECR(x)                             (((x) >> 0) & 0xF)
+#define   C_028A2C_DECR                                0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x028A30
+#define   S_028A30_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A30_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A30_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A30_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A30_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A30_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A30_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A30_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A30_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A30_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A30_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A30_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A30_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A30_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A30_STRIDE                              0xFFFF00FF
+#define   S_028A30_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A30_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A30_SHIFT                               0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x028A34
+#define   S_028A34_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A34_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A34_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A34_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A34_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A34_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A34_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A34_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A34_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A34_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A34_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A34_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A34_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A34_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A34_STRIDE                              0xFFFF00FF
+#define   S_028A34_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A34_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A34_SHIFT                               0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x028A38
+#define   S_028A38_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A38_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A38_X_CONV                              0xFFFFFFF0
+#define   S_028A38_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A38_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A38_X_OFFSET                            0xFFFFFF0F
+#define   S_028A38_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A38_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A38_Y_CONV                              0xFFFFF0FF
+#define   S_028A38_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A38_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A38_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A38_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A38_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A38_Z_CONV                              0xFFF0FFFF
+#define   S_028A38_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A38_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A38_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A38_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A38_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A38_W_CONV                              0xF0FFFFFF
+#define   S_028A38_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A38_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A38_W_OFFSET                            0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x028A3C
+#define   S_028A3C_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A3C_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A3C_X_CONV                              0xFFFFFFF0
+#define   S_028A3C_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A3C_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A3C_X_OFFSET                            0xFFFFFF0F
+#define   S_028A3C_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A3C_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A3C_Y_CONV                              0xFFFFF0FF
+#define   S_028A3C_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A3C_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A3C_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A3C_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A3C_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A3C_Z_CONV                              0xFFF0FFFF
+#define   S_028A3C_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A3C_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A3C_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A3C_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A3C_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A3C_W_CONV                              0xF0FFFFFF
+#define   S_028A3C_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A3C_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A3C_W_OFFSET                            0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_028A4C_PA_SC_MODE_CNTL                     0x028A4C
+#define   S_028A4C_MSAA_ENABLE(x)                      (((x) & 0x1) << 0)
+#define   G_028A4C_MSAA_ENABLE(x)                      (((x) >> 0) & 0x1)
+#define   C_028A4C_MSAA_ENABLE                         0xFFFFFFFE
+#define   S_028A4C_CLIPRECT_ENABLE(x)                  (((x) & 0x1) << 1)
+#define   G_028A4C_CLIPRECT_ENABLE(x)                  (((x) >> 1) & 0x1)
+#define   C_028A4C_CLIPRECT_ENABLE                     0xFFFFFFFD
+#define   S_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) & 0x1) << 2)
+#define   G_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) >> 2) & 0x1)
+#define   C_028A4C_LINE_STIPPLE_ENABLE                 0xFFFFFFFB
+#define   S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) & 0x1) << 3)
+#define   G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) >> 3) & 0x1)
+#define   C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB        0xFFFFFFF7
+#define   S_028A4C_WALK_ORDER_ENABLE(x)                (((x) & 0x1) << 4)
+#define   G_028A4C_WALK_ORDER_ENABLE(x)                (((x) >> 4) & 0x1)
+#define   C_028A4C_WALK_ORDER_ENABLE                   0xFFFFFFEF
+#define   S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) & 0x1) << 5)
+#define   G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) >> 5) & 0x1)
+#define   C_028A4C_HALVE_DETAIL_SAMPLE_PERF            0xFFFFFFDF
+#define   S_028A4C_WALK_SIZE(x)                        (((x) & 0x1) << 6)
+#define   G_028A4C_WALK_SIZE(x)                        (((x) >> 6) & 0x1)
+#define   C_028A4C_WALK_SIZE                           0xFFFFFFBF
+#define   S_028A4C_WALK_ALIGNMENT(x)                   (((x) & 0x1) << 7)
+#define   G_028A4C_WALK_ALIGNMENT(x)                   (((x) >> 7) & 0x1)
+#define   C_028A4C_WALK_ALIGNMENT                      0xFFFFFF7F
+#define   S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) & 0x1) << 8)
+#define   G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) >> 8) & 0x1)
+#define   C_028A4C_WALK_ALIGN8_PRIM_FITS_ST            0xFFFFFEFF
+#define   S_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) & 0x1) << 9)
+#define   G_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) >> 9) & 0x1)
+#define   C_028A4C_TILE_COVER_NO_SCISSOR               0xFFFFFDFF
+#define   S_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) & 0x1) << 10)
+#define   G_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) >> 10) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_HI_Z                  0xFFFFFBFF
+#define   S_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) & 0x1) << 11)
+#define   G_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) >> 11) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_DETAIL_MASK           0xFFFFF7FF
+#define   S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) & 0x1) << 12)
+#define   G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) >> 12) & 0x1)
+#define   C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE         0xFFFFEFFF
+#define   S_028A4C_TILE_COVER_DISABLE(x)               (((x) & 0x1) << 13)
+#define   G_028A4C_TILE_COVER_DISABLE(x)               (((x) >> 13) & 0x1)
+#define   C_028A4C_TILE_COVER_DISABLE                  0xFFFFDFFF
+#define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) & 0x1) << 14)
+#define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) >> 14) & 0x1)
+#define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE             0xFFFFBFFF
+#define   S_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) & 0x1) << 15)
+#define   G_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) >> 15) & 0x1)
+#define   C_028A4C_FORCE_EOV_TILE_ENABLE               0xFFFF7FFF
+#define   S_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) & 0x1) << 16)
+#define   G_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) >> 16) & 0x1)
+#define   C_028A4C_FORCE_EOV_REZ_ENABLE                0xFFFEFFFF
+#define   S_028A4C_PS_ITER_SAMPLE(x)                   (((x) & 0x1) << 17)
+#define   G_028A4C_PS_ITER_SAMPLE(x)                   (((x) >> 17) & 0x1)
+#define   C_028A4C_PS_ITER_SAMPLE                      0xFFFDFFFF
+#define R_028A84_VGT_PRIMITIVEID_EN                  0x028A84
+#define   S_028A84_PRIMITIVEID_EN(x)                   (((x) & 0x1) << 0)
+#define   G_028A84_PRIMITIVEID_EN(x)                   (((x) >> 0) & 0x1)
+#define   C_028A84_PRIMITIVEID_EN                      0xFFFFFFFE
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN          0x028A94
+#define   S_028A94_RESET_EN(x)                         (((x) & 0x1) << 0)
+#define   G_028A94_RESET_EN(x)                         (((x) >> 0) & 0x1)
+#define   C_028A94_RESET_EN                            0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0            0x028AA0
+#define   S_028AA0_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA0_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA0_STEP_RATE                           0x00000000
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1            0x028AA4
+#define   S_028AA4_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA4_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA4_STEP_RATE                           0x00000000
+#define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
+#define   S_028AB0_STREAMOUT(x)                        (((x) & 0x1) << 0)
+#define   G_028AB0_STREAMOUT(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB0_STREAMOUT                           0xFFFFFFFE
+#define R_028AB4_VGT_REUSE_OFF                       0x028AB4
+#define   S_028AB4_REUSE_OFF(x)                        (((x) & 0x1) << 0)
+#define   G_028AB4_REUSE_OFF(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB4_REUSE_OFF                           0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN                      0x028AB8
+#define   S_028AB8_VTX_CNT_EN(x)                       (((x) & 0x1) << 0)
+#define   G_028AB8_VTX_CNT_EN(x)                       (((x) >> 0) & 0x1)
+#define   C_028AB8_VTX_CNT_EN                          0xFFFFFFFE
+#define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
+#define   S_028B20_BUFFER_0_EN(x)                      (((x) & 0x1) << 0)
+#define   G_028B20_BUFFER_0_EN(x)                      (((x) >> 0) & 0x1)
+#define   C_028B20_BUFFER_0_EN                         0xFFFFFFFE
+#define   S_028B20_BUFFER_1_EN(x)                      (((x) & 0x1) << 1)
+#define   G_028B20_BUFFER_1_EN(x)                      (((x) >> 1) & 0x1)
+#define   C_028B20_BUFFER_1_EN                         0xFFFFFFFD
+#define   S_028B20_BUFFER_2_EN(x)                      (((x) & 0x1) << 2)
+#define   G_028B20_BUFFER_2_EN(x)                      (((x) >> 2) & 0x1)
+#define   C_028B20_BUFFER_2_EN                         0xFFFFFFFB
+#define   S_028B20_BUFFER_3_EN(x)                      (((x) & 0x1) << 3)
+#define   G_028B20_BUFFER_3_EN(x)                      (((x) >> 3) & 0x1)
+#define   C_028B20_BUFFER_3_EN                         0xFFFFFFF7
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX    0x028C20
+#define   S_028C20_S4_X(x)                             (((x) & 0xF) << 0)
+#define   G_028C20_S4_X(x)                             (((x) >> 0) & 0xF)
+#define   C_028C20_S4_X                                0xFFFFFFF0
+#define   S_028C20_S4_Y(x)                             (((x) & 0xF) << 4)
+#define   G_028C20_S4_Y(x)                             (((x) >> 4) & 0xF)
+#define   C_028C20_S4_Y                                0xFFFFFF0F
+#define   S_028C20_S5_X(x)                             (((x) & 0xF) << 8)
+#define   G_028C20_S5_X(x)                             (((x) >> 8) & 0xF)
+#define   C_028C20_S5_X                                0xFFFFF0FF
+#define   S_028C20_S5_Y(x)                             (((x) & 0xF) << 12)
+#define   G_028C20_S5_Y(x)                             (((x) >> 12) & 0xF)
+#define   C_028C20_S5_Y                                0xFFFF0FFF
+#define   S_028C20_S6_X(x)                             (((x) & 0xF) << 16)
+#define   G_028C20_S6_X(x)                             (((x) >> 16) & 0xF)
+#define   C_028C20_S6_X                                0xFFF0FFFF
+#define   S_028C20_S6_Y(x)                             (((x) & 0xF) << 20)
+#define   G_028C20_S6_Y(x)                             (((x) >> 20) & 0xF)
+#define   C_028C20_S6_Y                                0xFF0FFFFF
+#define   S_028C20_S7_X(x)                             (((x) & 0xF) << 24)
+#define   G_028C20_S7_X(x)                             (((x) >> 24) & 0xF)
+#define   C_028C20_S7_X                                0xF0FFFFFF
+#define   S_028C20_S7_Y(x)                             (((x) & 0xF) << 28)
+#define   G_028C20_S7_Y(x)                             (((x) >> 28) & 0xF)
+#define   C_028C20_S7_Y                                0x0FFFFFFF
+#define R_028C30_CB_CLRCMP_CONTROL                   0x028C30
+#define   S_028C30_CLRCMP_FCN_SRC(x)                   (((x) & 0x7) << 0)
+#define   G_028C30_CLRCMP_FCN_SRC(x)                   (((x) >> 0) & 0x7)
+#define   C_028C30_CLRCMP_FCN_SRC                      0xFFFFFFF8
+#define   S_028C30_CLRCMP_FCN_DST(x)                   (((x) & 0x7) << 8)
+#define   G_028C30_CLRCMP_FCN_DST(x)                   (((x) >> 8) & 0x7)
+#define   C_028C30_CLRCMP_FCN_DST                      0xFFFFF8FF
+#define   S_028C30_CLRCMP_FCN_SEL(x)                   (((x) & 0x3) << 24)
+#define   G_028C30_CLRCMP_FCN_SEL(x)                   (((x) >> 24) & 0x3)
+#define   C_028C30_CLRCMP_FCN_SEL                      0xFCFFFFFF
+#define R_028C34_CB_CLRCMP_SRC                       0x028C34
+#define   S_028C34_CLRCMP_SRC(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C34_CLRCMP_SRC(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C34_CLRCMP_SRC                          0x00000000
+#define R_028C38_CB_CLRCMP_DST                       0x028C38
+#define   S_028C38_CLRCMP_DST(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C38_CLRCMP_DST(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C38_CLRCMP_DST                          0x00000000
+#define R_028C3C_CB_CLRCMP_MSK                       0x028C3C
+#define   S_028C3C_CLRCMP_MSK(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C3C_CLRCMP_MSK(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C3C_CLRCMP_MSK                          0x00000000
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CR_DEST_BASE_ENA(x)                 (((x) & 0x1) << 15)
+#define   G_0085F0_CR_DEST_BASE_ENA(x)                 (((x) >> 15) & 0x1)
+#define   C_0085F0_CR_DEST_BASE_ENA                    0xFFFF7FFF
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+
+
+#define R_02812C_CB_CLEAR_ALPHA                      0x02812C
+#define   S_02812C_CLEAR_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_02812C_CLEAR_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02812C_CLEAR_ALPHA                         0x00000000
+#define R_028128_CB_CLEAR_BLUE                       0x028128
+#define   S_028128_CLEAR_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028128_CLEAR_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028128_CLEAR_BLUE                          0x00000000
+#define R_028124_CB_CLEAR_GREEN                      0x028124
+#define   S_028124_CLEAR_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028124_CLEAR_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028124_CLEAR_GREEN                         0x00000000
+#define R_028120_CB_CLEAR_RED                        0x028120
+#define   S_028120_CLEAR_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028120_CLEAR_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028120_CLEAR_RED                           0x00000000
+#define R_02842C_CB_FOG_BLUE                         0x02842C
+#define   S_02842C_FOG_BLUE(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_02842C_FOG_BLUE(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02842C_FOG_BLUE                            0x00000000
+#define R_028428_CB_FOG_GREEN                        0x028428
+#define   S_028428_FOG_GREEN(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028428_FOG_GREEN(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028428_FOG_GREEN                           0x00000000
+#define R_028424_CB_FOG_RED                          0x028424
+#define   S_028424_FOG_RED(x)                          (((x) & 0xFFFFFFFF) << 0)
+#define   G_028424_FOG_RED(x)                          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028424_FOG_RED                             0x00000000
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA         0x00A40C
+#define   S_00A40C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A40C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A40C_BORDER_ALPHA                        0x00000000
+#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE          0x00A408
+#define   S_00A408_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A408_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A408_BORDER_BLUE                         0x00000000
+#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN         0x00A404
+#define   S_00A404_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A404_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A404_BORDER_GREEN                        0x00000000
+#define R_00A400_TD_PS_SAMPLER0_BORDER_RED           0x00A400
+#define   S_00A400_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A400_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A400_BORDER_RED                          0x00000000
+#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA         0x00A60C
+#define   S_00A60C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A60C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A60C_BORDER_ALPHA                        0x00000000
+#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE          0x00A608
+#define   S_00A608_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A608_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A608_BORDER_BLUE                         0x00000000
+#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN         0x00A604
+#define   S_00A604_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A604_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A604_BORDER_GREEN                        0x00000000
+#define R_00A600_TD_VS_SAMPLER0_BORDER_RED           0x00A600
+#define   S_00A600_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A600_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A600_BORDER_RED                          0x00000000
+#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA         0x00A80C
+#define   S_00A80C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A80C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A80C_BORDER_ALPHA                        0x00000000
+#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE          0x00A808
+#define   S_00A808_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A808_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A808_BORDER_BLUE                         0x00000000
+#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN         0x00A804
+#define   S_00A804_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A804_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A804_BORDER_GREEN                        0x00000000
+#define R_00A800_TD_GS_SAMPLER0_BORDER_RED           0x00A800
+#define   S_00A800_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A800_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A800_BORDER_RED                          0x00000000
+#define R_030000_SQ_ALU_CONSTANT0_0                  0x030000
+#define   S_030000_X(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030000_X(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030000_X                                   0x00000000
+#define R_030004_SQ_ALU_CONSTANT1_0                  0x030004
+#define   S_030004_Y(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030004_Y(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030004_Y                                   0x00000000
+#define R_030008_SQ_ALU_CONSTANT2_0                  0x030008
+#define   S_030008_Z(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_Z(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_Z                                   0x00000000
+#define R_03000C_SQ_ALU_CONSTANT3_0                  0x03000C
+#define   S_03000C_W(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_W(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_W                                   0x00000000
+#define R_0287E4_VGT_DMA_BASE_HI                     0x0287E4
+#define R_0287E8_VGT_DMA_BASE                        0x0287E8
+
+#endif
-- 
cgit v1.2.3


From 6043ee6e62800f4f7d2c62756b4c91cbf2639061 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Aug 2010 15:16:53 +1000
Subject: r600g: kill event type magic number in winsys

these events have names, use them.
---
 src/gallium/winsys/r600/drm/r600_state.c | 6 +++---
 src/gallium/winsys/r600/drm/r600d.h      | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index d17d6e7954f..2facec75dec 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -233,7 +233,7 @@ static int r600_state_pm4_config(struct radeon_state *state)
 	state->pm4[state->cpm4++] = 0x80000000;
 	state->pm4[state->cpm4++] = 0x80000000;
 	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = 0x00000016;
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
 	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
 	state->pm4[state->cpm4++] = 0x00000010;
 	state->pm4[state->cpm4++] = 0x00028000;
@@ -246,7 +246,7 @@ static int r700_state_pm4_config(struct radeon_state *state)
 	state->pm4[state->cpm4++] = 0x80000000;
 	state->pm4[state->cpm4++] = 0x80000000;
 	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = 0x00000016;
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
 	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
 	state->pm4[state->cpm4++] = 0x00000010;
 	state->pm4[state->cpm4++] = 0x00028000;
@@ -314,7 +314,7 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
 	}
 	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = 0x00000016;
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
 	return 0;
 }
 
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 5d13378627e..235b2b3d976 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -82,6 +82,8 @@
 #define PKT3_SET_CTL_CONST                     0x6F
 #define PKT3_SURFACE_BASE_UPDATE               0x73
 
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
+
 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 #define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
 #define PKT_TYPE_C                      0x3FFFFFFF
-- 
cgit v1.2.3


From 63d010115c7972d854e0583f8f74e8d0c3407fcd Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Aug 2010 16:07:23 +1000
Subject: r600g: add occlusion query support

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c      |  34 +++--
 src/gallium/drivers/r600/r600_context.c   |  13 +-
 src/gallium/drivers/r600/r600_context.h   |  37 +++++-
 src/gallium/drivers/r600/r600_query.c     | 208 +++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/r600_state.c     |   1 -
 src/gallium/drivers/r600/radeon.h         |  30 +++--
 src/gallium/winsys/r600/drm/r600_state.c  |  36 ++++++
 src/gallium/winsys/r600/drm/r600_states.h |  25 ++--
 src/gallium/winsys/r600/drm/r600d.h       |   1 +
 src/gallium/winsys/r600/drm/radeon_ctx.c  |  36 +++++-
 10 files changed, 379 insertions(+), 42 deletions(-)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index db7aef7ebd2..aef4fbd9af9 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -32,8 +32,10 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static void r600_blitter_save_states(struct r600_context *rctx)
+static void r600_blitter_save_states(struct pipe_context *ctx)
 {
+	struct r600_context *rctx = r600_context(ctx);
+
 	util_blitter_save_blend(rctx->blitter, rctx->blend);
 	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
 	if (rctx->stencil_ref) {
@@ -47,8 +49,9 @@ static void r600_blitter_save_states(struct r600_context *rctx)
 	if (rctx->viewport) {
 		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
 	}
-	if (rctx->clip)
- 	    util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
+	if (rctx->clip) {
+		util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
+	}
 	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
 					rctx->vertex_buffer);
 
@@ -60,37 +63,44 @@ static void r600_blitter_save_states(struct r600_context *rctx)
 	rctx->rasterizer = NULL;
 	rctx->dsa = NULL;
 	rctx->vertex_elements = NULL;
+
+	/* suspend queries */
+	r600_queries_suspend(ctx);
 }
 
 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
-		       const float *rgba, double depth, unsigned stencil)
+			const float *rgba, double depth, unsigned stencil)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
 				fb->nr_cbufs, buffers, rgba, depth,
 				stencil);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
-static void r600_clear_render_target(struct pipe_context *pipe,
+static void r600_clear_render_target(struct pipe_context *ctx,
 				     struct pipe_surface *dst,
 				     const float *rgba,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(pipe);
+	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
-static void r600_clear_depth_stencil(struct pipe_context *pipe,
+static void r600_clear_depth_stencil(struct pipe_context *ctx,
 				     struct pipe_surface *dst,
 				     unsigned clear_flags,
 				     double depth,
@@ -98,14 +108,16 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(pipe);
+	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
 static void r600_resource_copy_region(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index edde80c660a..2f59a550f56 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -34,6 +34,7 @@
 #include "r600_resource.h"
 #include "r600d.h"
 
+
 static void r600_destroy_context(struct pipe_context *context)
 {
 	struct r600_context *rctx = r600_context(context);
@@ -46,26 +47,34 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
+	struct r600_query *rquery;
 	static int dc = 0;
 	char dname[256];
 
+	/* suspend queries */
+	r600_queries_suspend(rctx);
 	if (radeon_ctx_pm4(rctx->ctx))
-		return;
+		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
 	if (!rctx->ctx->cpm4)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 1)
+	if (dc < 10)
 		radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		rquery->flushed = true;
+	}
 	dc++;
 out:
 	rctx->ctx = radeon_ctx_decref(rctx->ctx);
 	rctx->ctx = radeon_ctx(rscreen->rw);
+	/* resume queries */
+	r600_queries_resume(rctx);
 }
 
 static void r600_init_config(struct r600_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 2ce29720d9c..900aa9fd0c2 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -30,9 +30,32 @@
 #include <tgsi/tgsi_parse.h>
 #include <tgsi/tgsi_util.h>
 #include <util/u_blitter.h>
+#include <util/u_double_list.h>
 #include "radeon.h"
 #include "r600_shader.h"
 
+#define R600_QUERY_STATE_STARTED	(1 << 0)
+#define R600_QUERY_STATE_ENDED		(1 << 1)
+#define R600_QUERY_STATE_SUSPENDED	(1 << 2)
+
+struct r600_query {
+	u64					result;
+	/* The kind of query. Currently only OQ is supported. */
+	unsigned				type;
+	/* How many results have been written, in dwords. It's incremented
+	 * after end_query and flush. */
+	unsigned				num_results;
+	/* if we've flushed the query */
+	boolean					flushed;
+	unsigned				state;
+	/* The buffer where query results are stored. */
+	struct radeon_bo			*buffer;
+	unsigned				buffer_size;
+	/* linked list of queries */
+	struct list_head			list;
+	struct radeon_state			*rstate;
+};
+
 /* XXX move this to a more appropriate place */
 union pipe_states {
 	struct pipe_rasterizer_state		rasterizer;
@@ -142,7 +165,8 @@ struct r600_context {
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
 	struct pipe_index_buffer	index_buffer;
-	struct pipe_blend_color         blend_color;
+	struct pipe_blend_color		blend_color;
+	struct list_head		query_list;
 };
 
 /* Convenience cast wrapper. */
@@ -151,6 +175,11 @@ static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
     return (struct r600_context*)pipe;
 }
 
+static INLINE struct r600_query* r600_query(struct pipe_query* q)
+{
+    return (struct r600_query*)q;
+}
+
 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state);
 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
@@ -179,4 +208,10 @@ extern int r600_pipe_shader_update(struct pipe_context *ctx,
 uint32_t r600_translate_texformat(enum pipe_format format,
 				  const unsigned char *swizzle_view, 
 				  uint32_t *word4_p, uint32_t *yuv_format_p);
+
+/* query */
+extern void r600_queries_resume(struct pipe_context *ctx);
+extern void r600_queries_suspend(struct pipe_context *ctx);
+
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 9b02ae680e7..5929606cd28 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -24,39 +24,233 @@
  *      Jerome Glisse
  *      Corbin Simpson
  */
+#include <errno.h>
 #include <util/u_inlines.h>
 #include <util/u_format.h>
 #include <util/u_memory.h>
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static struct pipe_query *r600_create_query(struct pipe_context *pipe, unsigned query_type)
+static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
 {
-	return NULL;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static void r600_destroy_query(struct pipe_context *pipe, struct pipe_query *query)
+static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *q;
+
+	if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
+		return NULL;
+
+	q = CALLOC_STRUCT(r600_query);
+	if (!q)
+		return NULL;
+
+	q->type = query_type;
+	LIST_ADDTAIL(&q->list, &rctx->query_list);
+	q->buffer_size = 4096;
+
+	q->buffer = radeon_bo(rscreen->rw, 0, q->buffer_size, 1, NULL);
+	if (!q->buffer) {
+		FREE(q);
+		return NULL;
+	}
+	return (struct pipe_query *)q;
+}
+
+static void r600_destroy_query(struct pipe_context *ctx,
+			       struct pipe_query *query)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_query *q = r600_query(query);
+
+	radeon_bo_decref(rscreen->rw, q->buffer);
+	LIST_DEL(&q->list);
 	FREE(query);
 }
 
-static void r600_begin_query(struct pipe_context *pipe, struct pipe_query *query)
+static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquery)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	u64 start, end;
+	u32 *results;
+	int i;
+
+	radeon_bo_wait(rscreen->rw, rquery->buffer);
+	radeon_bo_map(rscreen->rw, rquery->buffer);
+	results = rquery->buffer->data;
+	for (i = 0; i < rquery->num_results; i += 4) {
+		start = (u64)results[i] | (u64)results[i + 1] << 32;
+		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
+		if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
+			rquery->result += end - start;
+		}
+	}
+	radeon_bo_unmap(rscreen->rw, rquery->buffer);
+	rquery->num_results = 0;
 }
 
-static void r600_end_query(struct pipe_context *pipe, struct pipe_query *query)
+static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquery)
 {
+	struct r600_context *rctx = r600_context(ctx);
+
+	if (rquery->num_results >= ((rquery->buffer_size >> 2) - 2)) {
+		/* running out of space */
+		if (!rquery->flushed) {
+			ctx->flush(ctx, 0, NULL);
+		}
+		r600_query_result(ctx, rquery);
+	}
+	rquery->rstate = radeon_state_decref(rquery->rstate);
+	rquery->rstate = r600_query_begin(rctx, rquery);
+	rquery->flushed = false;
+}
+
+static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rquery)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	rquery->rstate = radeon_state_decref(rquery->rstate);
+	rquery->rstate = r600_query_end(rctx, rquery);
+	rquery->num_results += 16;
 }
 
-static boolean r600_get_query_result(struct pipe_context *pipe,
+static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery = r600_query(query);
+	int r;
+
+	rquery->state = R600_QUERY_STATE_STARTED;
+	rquery->num_results = 0;
+	rquery->flushed = false;
+	r600_query_resume(ctx, rquery);
+	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	if (r == -EBUSY) {
+		/* this shouldn't happen */
+		R600_ERR("had to flush while emitting end query\n");
+		ctx->flush(ctx, 0, NULL);
+		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	}
+}
+
+static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery = r600_query(query);
+	int r;
+
+	rquery->state &= ~R600_QUERY_STATE_STARTED;
+	rquery->state |= R600_QUERY_STATE_ENDED;
+	r600_query_suspend(ctx, rquery);
+	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	if (r == -EBUSY) {
+		/* this shouldn't happen */
+		R600_ERR("had to flush while emitting end query\n");
+		ctx->flush(ctx, 0, NULL);
+		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	}
+}
+
+void r600_queries_suspend(struct pipe_context *ctx)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery;
+	int r;
+
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		if (rquery->state & R600_QUERY_STATE_STARTED) {
+			r600_query_suspend(ctx, rquery);
+			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			if (r == -EBUSY) {
+				/* this shouldn't happen */
+				R600_ERR("had to flush while emitting end query\n");
+				ctx->flush(ctx, 0, NULL);
+				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			}
+		}
+		rquery->state |= R600_QUERY_STATE_SUSPENDED;
+	}
+}
+
+void r600_queries_resume(struct pipe_context *ctx)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery;
+	int r;
+
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		if (rquery->state & R600_QUERY_STATE_STARTED) {
+			r600_query_resume(ctx, rquery);
+			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			if (r == -EBUSY) {
+				/* this shouldn't happen */
+				R600_ERR("had to flush while emitting end query\n");
+				ctx->flush(ctx, 0, NULL);
+				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			}
+		}
+		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
+	}
+}
+
+static boolean r600_get_query_result(struct pipe_context *ctx,
 					struct pipe_query *query,
-					boolean wait, void *result)
+					boolean wait, void *vresult)
 {
+	struct r600_query *rquery = r600_query(query);
+	uint64_t *result = (uint64_t*)vresult;
+
+	if (!rquery->flushed) {
+		ctx->flush(ctx, 0, NULL);
+		rquery->flushed = true;
+	}
+	r600_query_result(ctx, rquery);
+	*result = rquery->result;
+	rquery->result = 0;
 	return TRUE;
 }
 
 void r600_init_query_functions(struct r600_context* rctx)
 {
+	LIST_INITHEAD(&rctx->query_list);
+
 	rctx->context.create_query = r600_create_query;
 	rctx->context.destroy_query = r600_destroy_query;
 	rctx->context.begin_query = r600_begin_query;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 7d2b61f9b01..3943ebacb36 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -268,7 +268,6 @@ static void r600_set_blend_color(struct pipe_context *ctx,
 static void r600_set_clip_state(struct pipe_context *ctx,
 				const struct pipe_clip_state *state)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_context_state *rstate;
 
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index d36c89d6a72..b2cc74f6967 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -151,6 +151,7 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon);
 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
 struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_pm4(struct radeon_ctx *ctx);
 int radeon_ctx_submit(struct radeon_ctx *ctx);
@@ -191,8 +192,8 @@ struct radeon_ctx {
  * R600/R700
  */
 
-#define R600_NSTATE				1286
-#define R600_NTYPE				33
+#define R600_NSTATE				1288
+#define R600_NTYPE				35
 
 #define R600_CONFIG				0
 #define R600_CONFIG_TYPE				0
@@ -252,14 +253,18 @@ struct radeon_ctx {
 #define R600_CB6_TYPE				27
 #define R600_CB7				1276
 #define R600_CB7_TYPE				28
-#define R600_DB				1277
-#define R600_DB_TYPE				29
-#define R600_CLIP				1278
-#define R600_CLIP_TYPE				30
-#define R600_VGT				1284
-#define R600_VGT_TYPE				31
-#define R600_DRAW				1285
-#define R600_DRAW_TYPE				32
+#define R600_QUERY_BEGIN			1277
+#define R600_QUERY_BEGIN_TYPE			29
+#define R600_QUERY_END				1278
+#define R600_QUERY_END_TYPE			30
+#define R600_DB					1279
+#define R600_DB_TYPE				31
+#define R600_CLIP				1280
+#define R600_CLIP_TYPE				32
+#define R600_VGT				1286
+#define R600_VGT_TYPE				33
+#define R600_DRAW				1287
+#define R600_DRAW_TYPE				34
 
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
@@ -653,4 +658,9 @@ struct radeon_ctx {
 #define R600_CLIP__PA_CL_UCP_W_0  3
 #define R600_CLIP_SIZE  4
 #define R600_CLIP_PM4 128
+/* R600 QUERY BEGIN/END */
+#define R600_QUERY__OFFSET			0
+#define R600_QUERY_SIZE				1
+#define R600_QUERY_PM4				128
+
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 2facec75dec..9b7c11bdc06 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -38,6 +38,8 @@ static int r600_state_pm4_shader(struct radeon_state *state);
 static int r600_state_pm4_draw(struct radeon_state *state);
 static int r600_state_pm4_config(struct radeon_state *state);
 static int r600_state_pm4_generic(struct radeon_state *state);
+static int r600_state_pm4_query_begin(struct radeon_state *state);
+static int r600_state_pm4_query_end(struct radeon_state *state);
 static int r700_state_pm4_config(struct radeon_state *state);
 static int r700_state_pm4_cb0(struct radeon_state *state);
 static int r700_state_pm4_db(struct radeon_state *state);
@@ -240,6 +242,40 @@ static int r600_state_pm4_config(struct radeon_state *state)
 	return r600_state_pm4_generic(state);
 }
 
+static int r600_state_pm4_query_begin(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
+static int r600_state_pm4_query_end(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
 static int r700_state_pm4_config(struct radeon_state *state)
 {
 	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 2d7a1d31c8c..b5365e4275a 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -479,6 +479,10 @@ static const struct radeon_register R600_DRAW_names[] = {
 	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
 };
 
+static const struct radeon_register R600_VGT_EVENT_names[] = {
+	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
+};
+
 static struct radeon_type R600_types[] = {
 	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
 	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
@@ -509,11 +513,12 @@ static struct radeon_type R600_types[] = {
 	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 static struct radeon_type R700_types[] = {
@@ -546,10 +551,12 @@ static struct radeon_type R700_types[] = {
 	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 235b2b3d976..e8c2dc0651c 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -82,6 +82,7 @@
 #define PKT3_SET_CTL_CONST                     0x6F
 #define PKT3_SURFACE_BASE_UPDATE               0x73
 
+#define EVENT_TYPE_ZPASS_DONE                  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 
 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 45b706bb0f9..bd050c4cf90 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -224,6 +224,41 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 	return 0;
 }
 
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
+{
+	void *tmp;
+	int r = 0;
+
+	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
+	if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+		return -EINVAL;
+	}
+	r = radeon_state_pm4(state);
+	if (r)
+		return r;
+	if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
+		/* need to flush */
+		return -EBUSY;
+	}
+	if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
+		fprintf(stderr, "%s single state too big %d, max %d\n",
+			__func__, state->cpm4, RADEON_CTX_MAX_PM4);
+		return -EINVAL;
+	}
+	tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
+	if (tmp == NULL)
+		return -ENOMEM;
+	ctx->state = tmp;
+	ctx->state[ctx->nstate++] = radeon_state_incref(state);
+	/* BEGIN/END query are balanced in the same cs so account for END
+	 * END query when scheduling BEGIN query
+	 */
+	if (state->type == R600_QUERY_BEGIN_TYPE) {
+		ctx->draw_cpm4 += state->cpm4 * 2;
+	}
+	return 0;
+}
+
 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
 	struct radeon_draw *pdraw = NULL;
@@ -366,7 +401,6 @@ printf("%d pm4\n", ctx->cpm4);
 		if (bo == NULL)
 			goto out_err;
 		size = bof_int32(ctx->bo[i]->size);
-printf("[%d] %d bo\n", i, size);
 		if (size == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "size", size))
-- 
cgit v1.2.3


From 50526e094f4c66957c7f74c190c35903bc82fb62 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 3 Sep 2010 14:38:41 +1000
Subject: r600g: add initial evergreen support

adds shader opcodes + assembler support (except ARL)
uses constant buffers
add interp instructions in fragment shader
adds all evergreen hw states
adds evergreen pm4 support.

this runs gears for me on my evergreen
---
 src/gallium/drivers/r600/Makefile            |    4 +-
 src/gallium/drivers/r600/eg_asm.c            |   84 ++
 src/gallium/drivers/r600/eg_hw_states.c      | 1071 +++++++++++++++++++
 src/gallium/drivers/r600/eg_sq.h             |  485 +++++++++
 src/gallium/drivers/r600/eg_state_inlines.h  |  434 ++++++++
 src/gallium/drivers/r600/eg_states_inc.h     |  521 ++++++++++
 src/gallium/drivers/r600/evergreend.h        | 1442 ++++++++++++++++++++++++++
 src/gallium/drivers/r600/r600_asm.c          |   33 +-
 src/gallium/drivers/r600/r600_asm.h          |    1 +
 src/gallium/drivers/r600/r600_context.c      |    6 +-
 src/gallium/drivers/r600/r600_context.h      |    7 +
 src/gallium/drivers/r600/r600_hw_states.c    |    1 +
 src/gallium/drivers/r600/r600_opcodes.h      |  222 +++-
 src/gallium/drivers/r600/r600_screen.c       |   12 +-
 src/gallium/drivers/r600/r600_shader.c       |  203 +++-
 src/gallium/drivers/r600/r600_sq.h           |   12 +-
 src/gallium/drivers/r600/r600_state.c        |   14 +-
 src/gallium/drivers/r600/r600_texture.c      |   34 +-
 src/gallium/drivers/r600/r700_asm.c          |    1 +
 src/gallium/drivers/r600/radeon.h            |    1 +
 src/gallium/winsys/r600/drm/eg_states.h      |  521 ++++++++++
 src/gallium/winsys/r600/drm/gen_eg_states.py |   39 +
 src/gallium/winsys/r600/drm/r600_state.c     |  198 +++-
 src/gallium/winsys/r600/drm/r600d.h          |    9 +
 src/gallium/winsys/r600/drm/radeon.c         |   10 +-
 25 files changed, 5303 insertions(+), 62 deletions(-)
 create mode 100644 src/gallium/drivers/r600/eg_asm.c
 create mode 100644 src/gallium/drivers/r600/eg_hw_states.c
 create mode 100644 src/gallium/drivers/r600/eg_sq.h
 create mode 100644 src/gallium/drivers/r600/eg_state_inlines.h
 create mode 100644 src/gallium/drivers/r600/eg_states_inc.h
 create mode 100644 src/gallium/drivers/r600/evergreend.h
 create mode 100644 src/gallium/winsys/r600/drm/eg_states.h
 create mode 100644 src/gallium/winsys/r600/drm/gen_eg_states.py

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile
index 707c2fd0f4f..a5249e09aa3 100644
--- a/src/gallium/drivers/r600/Makefile
+++ b/src/gallium/drivers/r600/Makefile
@@ -20,6 +20,8 @@ C_SOURCES = \
 	r600_texture.c \
 	r600_asm.c \
 	r700_asm.c \
-	r600_hw_states.c
+	r600_hw_states.c \
+	eg_asm.c \
+	eg_hw_states.c
 
 include ../../Makefile.template
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
new file mode 100644
index 00000000000..bc5dda43ed0
--- /dev/null
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "r600_asm.h"
+#include "r600_context.h"
+#include "util/u_memory.h"
+#include "eg_sq.h"
+#include "r600_opcodes.h"
+#include <stdio.h>
+#include <errno.h>
+
+int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
+{
+	unsigned id = cf->id;
+
+	switch (cf->inst) {
+	case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
+	case (EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
+		bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
+		  S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache0_mode);
+		bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+					S_SQ_CF_ALU_WORD1_BARRIER(1) |
+					S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
+		break;
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
+		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+					S_SQ_CF_WORD1_BARRIER(1) |
+					S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
+		break;
+	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+	case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
+			S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
+			S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
+			S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
+		bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
+			S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
+		break;
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+	case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
+		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+					S_SQ_CF_WORD1_BARRIER(1) |
+			                S_SQ_CF_WORD1_COND(cf->cond) |
+			                S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
+
+		break;
+	default:
+		R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+		return -EINVAL;
+	}
+	return 0;
+}
diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
new file mode 100644
index 00000000000..9e704f0de6f
--- /dev/null
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -0,0 +1,1071 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *           2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ *      Dave Airlie
+ */
+#include <util/u_inlines.h>
+#include <util/u_format.h>
+#include <util/u_memory.h>
+#include <util/u_blitter.h>
+#include "util/u_pack_color.h"
+#include "r600_screen.h"
+#include "r600_context.h"
+#include "r600_resource.h"
+#include "eg_state_inlines.h"
+#include "evergreend.h"
+
+#include "eg_states_inc.h"
+
+static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	int i;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
+	rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
+	rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
+	rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
+	rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
+	rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
+	rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
+
+	for (i = 0; i < 8; i++) {
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+		uint32_t bc = 0;
+
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		bc |= S_028780_BLEND_CONTROL_ENABLE(1);
+
+		bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
+			bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+		}
+
+		rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
+	}
+
+	radeon_state_pm4(rstate);
+}
+
+static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
+	    const struct pipe_clip_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
+
+	for (int i = 0; i < state->nr; i++) {
+		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
+		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
+		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
+		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
+	}
+	radeon_state_pm4(rstate);
+}
+
+static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_framebuffer_state *state, int cb)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	rstate->nbo = 1;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_028C70_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
+	color_info = S_028C70_FORMAT(format) |
+		S_028C70_COMP_SWAP(swap) |
+		S_028C70_BLEND_CLAMP(1) |
+		S_028C70_SOURCE_FORMAT(1) |
+		S_028C70_NUMBER_TYPE(ntype);
+
+	rstate->states[EG_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
+	rstate->states[EG_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[EG_CB0__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
+	rstate->states[EG_CB0__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
+	rstate->states[EG_CB0__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[EG_CB0__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
+
+	radeon_state_pm4(rstate);
+}
+
+static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_framebuffer_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level;
+	unsigned pitch, slice, format;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
+	if (state->zsbuf == NULL)
+		return;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tilled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	level = state->zsbuf->level;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+	rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
+	rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
+	rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
+	radeon_state_pm4(rstate);
+}
+
+static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
+{
+	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	const struct pipe_clip_state *clip = NULL;
+	struct r600_screen *rscreen = rctx->screen;
+	float offset_units = 0, offset_scale = 0;
+	char depth = 0;
+	unsigned offset_db_fmt_cntl = 0;
+	unsigned tmp;
+	unsigned prov_vtx = 1;
+
+	if (rctx->clip)
+		clip = &rctx->clip->state.clip;
+	if (fb->zsbuf) {
+		offset_units = state->offset_units;
+		offset_scale = state->offset_scale * 12.0f;
+		switch (fb->zsbuf->texture->format) {
+		case PIPE_FORMAT_Z24X8_UNORM:
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			depth = -24;
+			offset_units *= 2.0f;
+			break;
+		case PIPE_FORMAT_Z32_FLOAT:
+			depth = -23;
+			offset_units *= 1.0f;
+			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			depth = -16;
+			offset_units *= 4.0f;
+			break;
+		default:
+			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
+			return;
+		}
+	}
+	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+
+	if (state->flatshade_first)
+		prov_vtx = 0;
+
+	rctx->flat_shade = state->flatshade;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
+	rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
+	if (rctx->flat_shade)
+		rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
+	if (state->sprite_coord_enable) {
+		rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+				S_0286D4_PNT_SPRITE_ENA(1) |
+				S_0286D4_PNT_SPRITE_OVRD_X(2) |
+				S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+				S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+				S_0286D4_PNT_SPRITE_OVRD_W(1);
+		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+			rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+					S_0286D4_PNT_SPRITE_TOP_1(1);
+		}
+	}
+	rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
+	if (clip) {
+		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
+		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
+		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
+	}
+	rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
+		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+		S_028814_FACE(!state->front_ccw) |
+		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
+	rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
+			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
+	rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
+	/* point size 12.4 fixed point */
+	tmp = (unsigned)(state->point_size * 8.0);
+	rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
+	rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
+	rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
+	rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
+
+	rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
+	rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
+	rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
+	rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
+	rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
+	rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
+	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
+	radeon_state_pm4(rstate);
+}
+
+static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
+{
+	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
+	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	struct r600_screen *rscreen = rctx->screen;
+	unsigned minx, maxx, miny, maxy;
+	u32 tl, br;
+
+	if (state == NULL) {
+		minx = 0;
+		miny = 0;
+		maxx = fb->cbufs[0]->width;
+		maxy = fb->cbufs[0]->height;
+	} else {
+		minx = state->minx;
+		miny = state->miny;
+		maxx = state->maxx;
+		maxy = state->maxy;
+	}
+	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
+	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
+	/* screen scissor has no WINDOW OFFSET */
+	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
+	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
+	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
+	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
+	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
+	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
+	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
+	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
+	radeon_state_pm4(rstate);
+}
+
+static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
+	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
+	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
+	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
+	rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+	radeon_state_pm4(rstate);
+}
+
+static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
+{
+	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
+	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
+	struct r600_screen *rscreen = rctx->screen;
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+	struct r600_shader *rshader;
+	struct r600_query *rquery;
+	boolean query_running;
+	int i;
+
+	if (rctx->ps_shader == NULL) {
+		return;
+	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
+
+	db_shader_control = 0x210;
+	rshader = &rctx->ps_shader->shader;
+	if (rshader->uses_kill)
+		db_shader_control |= (1 << 6);
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			db_shader_control |= 1;
+	}
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+	/* set stencil enable */
+
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+			stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
+		}
+	}
+
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+		alpha_ref = fui(state->alpha.ref_value);
+	}
+
+	db_render_control = 0;
+///	db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
+///		S_028D0C_DEPTH_COMPRESS_DISABLE(1);
+	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+
+	query_running = false;
+
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		if (rquery->state & R600_QUERY_STATE_STARTED) {
+			query_running = true;
+		}
+	}
+
+	if (query_running) {
+		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
+		if (rscreen->chip_class == R700)
+			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
+	}
+
+	rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
+	rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
+	rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
+	rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
+	rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
+	rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
+	//	rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
+	//	rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
+	rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
+	rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
+	rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
+	rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
+	rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
+	  
+	rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
+	rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
+	rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
+	radeon_state_pm4(rstate);
+}
+
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+
+static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
+				const struct pipe_sampler_state *state, unsigned id)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	union util_color uc;
+
+	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
+	if (uc.ui) {
+		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
+		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
+		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
+		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
+	}
+	radeon_state_pm4(rstate);
+}
+
+static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_sampler_state *state, unsigned id)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	union util_color uc;
+
+	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
+	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+	                S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+	                S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
+	/* FIXME LOD it depends on texture base level ... */
+	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+		S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
+
+	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = 
+		S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
+S_03C008_TYPE(1);
+	radeon_state_pm4(rstate);
+
+}
+
+
+static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
+			const struct pipe_sampler_view *view, unsigned id)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_screen *rscreen = rctx->screen;
+	const struct util_format_description *desc;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
+	unsigned format;
+	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+	unsigned char swizzle[4];
+	int r;
+
+	rstate->cpm4 = 0;
+	swizzle[0] = view->swizzle_r;
+	swizzle[1] = view->swizzle_g;
+	swizzle[2] = view->swizzle_b;
+	swizzle[3] = view->swizzle_a;
+	format = r600_translate_texformat(view->texture->format,
+					  swizzle,
+					  &word4, &yuv_format);
+	if (format == ~0) {
+		return;
+	}
+	desc = util_format_description(view->texture->format);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", view->texture->format);
+		return;
+	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
+	tmp = (struct r600_resource_texture*)view->texture;
+	rbuffer = &tmp->resource;
+	if (tmp->depth) {
+		r = r600_texture_from_depth(ctx, tmp, view->first_level);
+		if (r) {
+			return;
+		}
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+	} else {
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	}
+	rstate->nbo = 2;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
+
+	pitch = (tmp->pitch[0] / tmp->bpt);
+	pitch = (pitch + 0x7) & ~0x7;
+
+	/* FIXME properly handle first level != 0 */
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
+			S_030000_DIM(r600_tex_dim(view->texture->target)) |
+			S_030000_PITCH((pitch / 8) - 1) |
+			S_030000_TEX_WIDTH(view->texture->width0 - 1);
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
+		S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
+		S_030004_TEX_DEPTH(view->texture->depth0 - 1);
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
+		        word4 | 
+			S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
+			S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
+			S_030010_REQUEST_SIZE(1) |
+			S_030010_BASE_LEVEL(view->first_level);
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
+			S_030014_LAST_LEVEL(view->last_level) |
+			S_030014_BASE_ARRAY(0) |
+			S_030014_LAST_ARRAY(0);
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
+	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
+			S_03001C_DATA_FORMAT(format) |
+			S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
+	radeon_state_pm4(rstate);
+}
+
+static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
+	uint32_t color_control, target_mask, shader_mask;
+	int i;
+
+	target_mask = 0;
+	shader_mask = 0;
+	color_control = S_028808_MODE(1);
+
+	for (i = 0; i < nr_cbufs; i++) {
+		shader_mask |= 0xf << (i * 4);
+	}
+
+	if (pbs->logicop_enable) {
+		color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
+	} else {
+		color_control |= (0xcc << 16);
+	}
+
+	if (pbs->independent_blend_enable) {
+		for (i = 0; i < nr_cbufs; i++) {
+			target_mask |= (pbs->rt[i].colormask << (4 * i));
+		}
+	} else {
+		for (i = 0; i < nr_cbufs; i++) {
+			target_mask |= (pbs->rt[0].colormask << (4 * i));
+		}
+	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
+	rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
+	rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
+	rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
+	rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
+	rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
+	rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+	radeon_state_pm4(rstate);
+}
+
+
+static void eg_init_config(struct r600_context *rctx)
+{
+	int ps_prio;
+	int vs_prio;
+	int gs_prio;
+	int es_prio;
+	int hs_prio, cs_prio, ls_prio;
+	int num_ps_gprs;
+	int num_vs_gprs;
+	int num_gs_gprs;
+	int num_es_gprs;
+	int num_hs_gprs;
+	int num_ls_gprs;
+	int num_temp_gprs;
+	int num_ps_threads;
+	int num_vs_threads;
+	int num_gs_threads;
+	int num_es_threads;
+	int num_hs_threads;
+	int num_ls_threads;
+	int num_ps_stack_entries;
+	int num_vs_stack_entries;
+	int num_gs_stack_entries;
+	int num_es_stack_entries;
+	int num_hs_stack_entries;
+	int num_ls_stack_entries;
+	enum radeon_family family;
+
+	family = radeon_get_family(rctx->rw);
+	ps_prio = 0;
+	vs_prio = 1;
+	gs_prio = 2;
+	es_prio = 3;
+	hs_prio = 0;
+	ls_prio = 0;
+	cs_prio = 0;
+
+	switch (family) {
+	case CHIP_CEDAR:
+	default:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 96;
+		num_vs_threads = 16;
+		num_gs_threads = 16;
+		num_es_threads = 16;
+		num_hs_threads = 16;
+		num_ls_threads = 16;
+		num_ps_stack_entries = 42;
+		num_vs_stack_entries = 42;
+		num_gs_stack_entries = 42;
+		num_es_stack_entries = 42;
+		num_hs_stack_entries = 42;
+		num_ls_stack_entries = 42;
+		break;
+	case CHIP_REDWOOD:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 42;
+		num_vs_stack_entries = 42;
+		num_gs_stack_entries = 42;
+		num_es_stack_entries = 42;
+		num_hs_stack_entries = 42;
+		num_ls_stack_entries = 42;
+		break;
+	case CHIP_JUNIPER:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 85;
+		num_vs_stack_entries = 85;
+		num_gs_stack_entries = 85;
+		num_es_stack_entries = 85;
+		num_hs_stack_entries = 85;
+		num_ls_stack_entries = 85;
+		break;
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 85;
+		num_vs_stack_entries = 85;
+		num_gs_stack_entries = 85;
+		num_es_stack_entries = 85;
+		num_hs_stack_entries = 85;
+		num_ls_stack_entries = 85;
+		break;
+	}
+
+	radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
+
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
+	switch (family) {
+	case CHIP_CEDAR:
+		break;
+	default:
+		rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		break;
+	}
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
+
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
+	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
+
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
+
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
+	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
+
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
+	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
+
+	rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
+
+	rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
+
+	rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
+	rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
+	rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
+
+	rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+
+	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
+	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
+
+	rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
+	rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+//	rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
+//	rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
+	rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
+	
+	radeon_state_pm4(&rctx->config);
+}
+
+static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
+			    uint32_t stride, uint32_t format)
+{
+	struct radeon_state *vs_resource = &rctx->vs_resource[id];
+	struct r600_screen *rscreen = rctx->screen;
+
+	radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
+	vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	vs_resource->nbo = 1;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
+		S_030008_DATA_FORMAT(format);
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
+		S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
+		S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
+		S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
+	  
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
+	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
+	vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
+	return radeon_state_pm4(vs_resource);
+}
+
+static int eg_draw_vgt_init(struct r600_context *rctx, struct radeon_state *draw,
+			    struct r600_resource *rbuffer,
+			    uint32_t count, int vgt_draw_initiator)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	
+	radeon_state_init(draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
+	draw->states[EG_DRAW__VGT_NUM_INDICES] = count;
+	draw->states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	if (rbuffer) {
+		draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->nbo = 1;
+	}
+	return radeon_state_pm4(draw);
+}
+
+static int eg_draw_vgt_prim(struct r600_context *rctx, struct radeon_state *vgt,
+			    uint32_t prim, uint32_t start, uint32_t vgt_dma_index_type)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	radeon_state_init(vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
+	vgt->states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	vgt->states[EG_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	vgt->states[EG_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	vgt->states[EG_VGT__VGT_INDX_OFFSET] = start;
+	vgt->states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	vgt->states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	vgt->states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	vgt->states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	vgt->states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	return radeon_state_pm4(vgt);
+}
+
+
+static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
+			  struct radeon_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	const struct pipe_rasterizer_state *rasterizer;
+	struct r600_shader *rshader = &rpshader->shader;
+	unsigned i, tmp, exports_ps, num_cout;
+	boolean have_pos = FALSE;
+
+	rasterizer = &rctx->rasterizer->state.rasterizer;
+
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
+	for (i = 0; i < rshader->ninput; i++) {
+		tmp = S_028644_SEMANTIC(i);
+		tmp |= S_028644_SEL_CENTROID(1);
+		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+			have_pos = TRUE;
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
+		if (rasterizer->sprite_coord_enable & (1 << i)) {
+			tmp |= S_028644_PT_SPRITE_TEX(1);
+		}
+		state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
+	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			exports_ps |= (1 << (num_cout+1));
+			num_cout++;
+		}
+	}
+	if (!exports_ps) {
+		/* always at least export 1 component per pixel */
+		exports_ps = 2;
+	}
+	state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
+							S_0286CC_PERSP_GRADIENT_ENA(1);
+	if (have_pos) {
+		state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1);
+		state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
+	}
+	state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
+	state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
+		S_028844_STACK_SIZE(rshader->bc.nstack);
+	state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
+	state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
+	  S_0286E0_LINEAR_CENTROID_ENA(1); 
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 1;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	return radeon_state_pm4(state);
+}
+
+static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
+			  struct radeon_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;	
+	struct r600_shader *rshader = &rpshader->shader;
+	unsigned i, tmp;
+
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
+	for (i = 0; i < 10; i++) {
+		state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
+	}
+	/* so far never got proper semantic id from tgsi */
+	for (i = 0; i < 32; i++) {
+		tmp = i << ((i & 3) * 8);
+		state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
+	}
+	state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
+	state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
+		S_028860_STACK_SIZE(rshader->bc.nstack);
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 2;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	return radeon_state_pm4(state);
+}
+
+struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
+	.blend = eg_blend,
+	.ucp = eg_ucp,
+	.cb = eg_cb,
+	.db = eg_db,
+	.rasterizer = eg_rasterizer,
+	.scissor = eg_scissor,
+	.viewport = eg_viewport,
+	.dsa = eg_dsa,
+	.sampler_border = eg_sampler_border,
+	.sampler = eg_sampler,
+	.resource = eg_resource,
+	.cb_cntl = eg_cb_cntl,
+	.vs_resource = eg_vs_resource,
+	.vgt_init = eg_draw_vgt_init,
+	.vgt_prim = eg_draw_vgt_prim,
+	.vs_shader = eg_vs_shader,
+	.ps_shader = eg_ps_shader,
+	.init_config = eg_init_config,
+};
+
+void eg_set_constant_buffer(struct pipe_context *ctx,
+			    uint shader, uint index,
+			    struct pipe_resource *buffer)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned nconstant = 0, type, shader_class, size;
+	struct radeon_state *rstate, *rstates;
+	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+
+	type = R600_STATE_CBUF;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		shader_class = R600_SHADER_VS;
+		rstates = rctx->vs_constant;
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		shader_class = R600_SHADER_PS;
+		rstates = rctx->ps_constant;
+		break;
+	default:
+		R600_ERR("unsupported %d\n", shader);
+		return;
+	}
+
+	rstate = &rstates[0];
+
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+	nconstant = buffer->width0 / 16;
+	size = ALIGN_DIVUP(nconstant, 16);
+
+	radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
+	rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
+	rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
+
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	if (radeon_state_pm4(rstate))
+		return;
+	radeon_draw_bind(&rctx->draw, rstate);
+}
diff --git a/src/gallium/drivers/r600/eg_sq.h b/src/gallium/drivers/r600/eg_sq.h
new file mode 100644
index 00000000000..f80e8bd3aaf
--- /dev/null
+++ b/src/gallium/drivers/r600/eg_sq.h
@@ -0,0 +1,485 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef EG_SQ_H
+#define EG_SQ_H
+
+#define P_SQ_CF_WORD0
+#define   S_SQ_CF_WORD0_ADDR(x)                                      (((x) & 0xFFFFFF) << 0)
+#define   G_SQ_CF_WORD0_ADDR(x)                                      (((x) >> 0) & 0xFFFFFF)
+#define   C_SQ_CF_WORD0_ADDR                                         0x00000000
+#define   S_SQ_CF_WORD0_JUMPTABLE_SEL(x)                             (((x) & 0x7) << 24)
+#define   G_SQ_CF_WORD0_JUMPTABLE_SEL(x)                             (((x) >> 24) & 0x7)
+#define   C_SQ_CF_WORD0_JUMPTABLE_SEL                                0xF8FFFFFF
+#define P_SQ_CF_WORD1
+#define   S_SQ_CF_WORD1_POP_COUNT(x)                                 (((x) & 0x7) << 0)
+#define   G_SQ_CF_WORD1_POP_COUNT(x)                                 (((x) >> 0) & 0x7)
+#define   C_SQ_CF_WORD1_POP_COUNT                                    0xFFFFFFF8
+#define   S_SQ_CF_WORD1_CF_CONST(x)                                  (((x) & 0x1F) << 3)
+#define   G_SQ_CF_WORD1_CF_CONST(x)                                  (((x) >> 3) & 0x1F)
+#define   C_SQ_CF_WORD1_CF_CONST                                     0xFFFFFF07
+#define   S_SQ_CF_WORD1_COND(x)                                      (((x) & 0x3) << 8)
+#define   G_SQ_CF_WORD1_COND(x)                                      (((x) >> 8) & 0x3)
+#define   C_SQ_CF_WORD1_COND                                         0xFFFFFCFF
+#define   S_SQ_CF_WORD1_COUNT(x)                                     (((x) & 0x3f) << 10)
+#define   G_SQ_CF_WORD1_COUNT(x)                                     (((x) >> 10) & 0x3f)
+#define   C_SQ_CF_WORD1_COUNT                                        0xFFFF03FF
+#define   S_SQ_CF_WORD1_VALID_PIXEL_MODE(x)                          (((x) & 0x1) << 20)
+#define   G_SQ_CF_WORD1_VALID_PIXEL_MODE(x)                          (((x) >> 20) & 0x1)
+#define   C_SQ_CF_WORD1_VALID_PIXEL_MODE                             0xFFEFFFFF
+#define   S_SQ_CF_WORD1_END_OF_PROGRAM(x)                            (((x) & 0x1) << 21)
+#define   G_SQ_CF_WORD1_END_OF_PROGRAM(x)                            (((x) >> 21) & 0x1)
+#define   C_SQ_CF_WORD1_END_OF_PROGRAM                               0xFFDFFFFF
+
+#define   S_SQ_CF_WORD1_CF_INST(x)                                   (((x) & 0xFF) << 22)
+#define   G_SQ_CF_WORD1_CF_INST(x)                                   (((x) >> 22) & 0xFF)
+#define   C_SQ_CF_WORD1_CF_INST                                      0xC03FFFFF
+
+#define   S_SQ_CF_WORD1_WHOLE_QUAD_MODE(x)                           (((x) & 0x1) << 30)
+#define   G_SQ_CF_WORD1_WHOLE_QUAD_MODE(x)                           (((x) >> 30) & 0x1)
+#define   C_SQ_CF_WORD1_WHOLE_QUAD_MODE                              0xBFFFFFFF
+#define   S_SQ_CF_WORD1_BARRIER(x)                                   (((x) & 0x1) << 31)
+#define   G_SQ_CF_WORD1_BARRIER(x)                                   (((x) >> 31) & 0x1)
+#define   C_SQ_CF_WORD1_BARRIER                                      0x7FFFFFFF
+
+/* done */
+#define P_SQ_CF_ALU_WORD0
+#define   S_SQ_CF_ALU_WORD0_ADDR(x)                                  (((x) & 0x3FFFFF) << 0)
+#define   G_SQ_CF_ALU_WORD0_ADDR(x)                                  (((x) >> 0) & 0x3FFFFF)
+#define   C_SQ_CF_ALU_WORD0_ADDR                                     0xFFC00000
+#define   S_SQ_CF_ALU_WORD0_KCACHE_BANK0(x)                          (((x) & 0xF) << 22)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_BANK0(x)                          (((x) >> 22) & 0xF)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_BANK0                             0xFC3FFFFF
+#define   S_SQ_CF_ALU_WORD0_KCACHE_BANK1(x)                          (((x) & 0xF) << 26)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_BANK1(x)                          (((x) >> 26) & 0xF)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_BANK1                             0xC3FFFFFF
+#define   S_SQ_CF_ALU_WORD0_KCACHE_MODE0(x)                          (((x) & 0x3) << 30)
+#define   G_SQ_CF_ALU_WORD0_KCACHE_MODE0(x)                          (((x) >> 30) & 0x3)
+#define   C_SQ_CF_ALU_WORD0_KCACHE_MODE0                             0x3FFFFFFF
+#define P_SQ_CF_ALU_WORD1
+#define   S_SQ_CF_ALU_WORD1_KCACHE_MODE1(x)                          (((x) & 0x3) << 0)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_MODE1(x)                          (((x) >> 0) & 0x3)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_MODE1                             0xFFFFFFFC
+#define   S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x)                          (((x) & 0xFF) << 2)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(x)                          (((x) >> 2) & 0xFF)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_ADDR0                             0xFFFFFC03
+#define   S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x)                          (((x) & 0xFF) << 10)
+#define   G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(x)                          (((x) >> 10) & 0xFF)
+#define   C_SQ_CF_ALU_WORD1_KCACHE_ADDR1                             0xFFFC03FF
+#define   S_SQ_CF_ALU_WORD1_COUNT(x)                                 (((x) & 0x7F) << 18)
+#define   G_SQ_CF_ALU_WORD1_COUNT(x)                                 (((x) >> 18) & 0x7F)
+#define   C_SQ_CF_ALU_WORD1_COUNT                                    0xFE03FFFF
+#define   S_SQ_CF_ALU_WORD1_ALT_CONST(x)                             (((x) & 0x1) << 25)
+#define   G_SQ_CF_ALU_WORD1_ALT_CONST(x)                             (((x) >> 25) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_ALT_CONST                                0xFDFFFFFF
+#define   S_SQ_CF_ALU_WORD1_CF_INST(x)                               (((x) & 0xF) << 26)
+#define   G_SQ_CF_ALU_WORD1_CF_INST(x)                               (((x) >> 26) & 0xF)
+#define   C_SQ_CF_ALU_WORD1_CF_INST                                  0xC3FFFFFF
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU                         0x00000008
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE             0x00000009
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER               0x0000000A
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER              0x0000000B
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED                    0x0000000C
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE                0x0000000D
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK                   0x0000000E
+#define     V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER              0x0000000F
+#define   S_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x)                       (((x) & 0x1) << 30)
+#define   G_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE(x)                       (((x) >> 30) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE                          0xBFFFFFFF
+#define   S_SQ_CF_ALU_WORD1_BARRIER(x)                               (((x) & 0x1) << 31)
+#define   G_SQ_CF_ALU_WORD1_BARRIER(x)                               (((x) >> 31) & 0x1)
+#define   C_SQ_CF_ALU_WORD1_BARRIER                                  0x7FFFFFFF
+/* extended TODO */
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD0
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x)                   (((x) & 0x1FFF) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(x)                   (((x) >> 0) & 0x1FFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE                      0xFFFFE000
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x)                         (((x) & 0x3) << 13)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(x)                         (((x) >> 13) & 0x3)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_TYPE                            0xFFFF9FFF
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL               0x00000000
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS                 0x00000001
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM               0x00000002
+#define     V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK       0x00000003
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x)                       (((x) & 0x7F) << 15)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(x)                       (((x) >> 15) & 0x7F)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR                          0xFFC07FFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x)                       (((x) & 0x1) << 22)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL(x)                       (((x) >> 22) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_RW_REL                          0xFFBFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x)                    (((x) & 0x7F) << 23)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(x)                    (((x) >> 23) & 0x7F)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR                       0xC07FFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x)                    (((x) & 0x3) << 30)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(x)                    (((x) >> 30) & 0x3)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE                       0x3FFFFFFF
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD1
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x)                  (((x) & 0xF) << 16)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(x)                  (((x) >> 16) & 0xF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT                     0xFFF0FFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x)             (((x) & 0x1) << 20)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE(x)             (((x) >> 20) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE                0xFFEFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x)               (((x) & 0x1) << 21)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(x)               (((x) >> 21) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM                  0xFFDFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) & 0xFF) << 22)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) >> 22) & 0xFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST                         0xC03FFFFF
+
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x)                         (((x) & 0x1) << 30)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_MARK(x)                         (((x) >> 30) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE                 0xBFFFFFFF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x)                      (((x) & 0x1) << 31)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(x)                      (((x) >> 31) & 0x1)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER                         0x7FFFFFFF
+
+/* done */
+#define P_SQ_CF_ALLOC_EXPORT_WORD1_BUF
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x)               (((x) & 0xFFF) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(x)               (((x) >> 0) & 0xFFF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE                  0xFFFFF000
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x)                (((x) & 0xF) << 12)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(x)                (((x) >> 12) & 0xF)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK                   0xFFFF0FFF
+#define P_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x)                   (((x) & 0x7) << 0)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(x)                   (((x) >> 0) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X                      0xFFFFFFF8
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x)                   (((x) & 0x7) << 3)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(x)                   (((x) >> 3) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y                      0xFFFFFFC7
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x)                   (((x) & 0x7) << 6)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(x)                   (((x) >> 6) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z                      0xFFFFFE3F
+#define   S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x)                   (((x) & 0x7) << 9)
+#define   G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(x)                   (((x) >> 9) & 0x7)
+#define   C_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W                      0xFFFFF1FF
+
+/* done */
+#define P_SQ_ALU_WORD0
+#define   S_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) & 0x1FF) << 0)
+#define   G_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) >> 0) & 0x1FF)
+#define   C_SQ_ALU_WORD0_SRC0_SEL                                    0xFFFFFE00
+
+/*
+ * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
+ * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
+ * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
+ * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
+ * 248  SQ_ALU_SRC_0: special constant 0.0.
+ * 249  SQ_ALU_SRC_1: special constant 1.0 float.
+ * 250  SQ_ALU_SRC_1_INT: special constant 1 integer.
+ * 251  SQ_ALU_SRC_M_1_INT: special constant -1 integer.
+ * 252  SQ_ALU_SRC_0_5: special constant 0.5 float.
+ * 253  SQ_ALU_SRC_LITERAL: literal constant.
+ * 254  SQ_ALU_SRC_PV: previous vector result.
+ * 255  SQ_ALU_SRC_PS: previous scalar result.
+ */
+#define     V_SQ_ALU_SRC_0                                           0x000000F8
+#define     V_SQ_ALU_SRC_1                                           0x000000F9
+#define     V_SQ_ALU_SRC_1_INT                                       0x000000FA
+#define     V_SQ_ALU_SRC_M_1_INT                                     0x000000FB
+#define     V_SQ_ALU_SRC_0_5                                         0x000000FC
+#define     V_SQ_ALU_SRC_LITERAL                                     0x000000FD
+#define   S_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) & 0x1) << 9)
+#define   G_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) >> 9) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC0_REL                                    0xFFFFFDFF
+#define   S_SQ_ALU_WORD0_SRC0_CHAN(x)                                (((x) & 0x3) << 10)
+#define   G_SQ_ALU_WORD0_SRC0_CHAN(x)                                (((x) >> 10) & 0x3)
+#define   C_SQ_ALU_WORD0_SRC0_CHAN                                   0xFFFFF3FF
+#define   S_SQ_ALU_WORD0_SRC0_NEG(x)                                 (((x) & 0x1) << 12)
+#define   G_SQ_ALU_WORD0_SRC0_NEG(x)                                 (((x) >> 12) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC0_NEG                                    0xFFFFEFFF
+#define   S_SQ_ALU_WORD0_SRC1_SEL(x)                                 (((x) & 0x1FF) << 13)
+#define   G_SQ_ALU_WORD0_SRC1_SEL(x)                                 (((x) >> 13) & 0x1FF)
+#define   C_SQ_ALU_WORD0_SRC1_SEL                                    0xFFC01FFF
+#define   S_SQ_ALU_WORD0_SRC1_REL(x)                                 (((x) & 0x1) << 22)
+#define   G_SQ_ALU_WORD0_SRC1_REL(x)                                 (((x) >> 22) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC1_REL                                    0xFFBFFFFF
+#define   S_SQ_ALU_WORD0_SRC1_CHAN(x)                                (((x) & 0x3) << 23)
+#define   G_SQ_ALU_WORD0_SRC1_CHAN(x)                                (((x) >> 23) & 0x3)
+#define   C_SQ_ALU_WORD0_SRC1_CHAN                                   0xFE7FFFFF
+#define   S_SQ_ALU_WORD0_SRC1_NEG(x)                                 (((x) & 0x1) << 25)
+#define   G_SQ_ALU_WORD0_SRC1_NEG(x)                                 (((x) >> 25) & 0x1)
+#define   C_SQ_ALU_WORD0_SRC1_NEG                                    0xFDFFFFFF
+#define   S_SQ_ALU_WORD0_INDEX_MODE(x)                               (((x) & 0x7) << 26)
+#define   G_SQ_ALU_WORD0_INDEX_MODE(x)                               (((x) >> 26) & 0x7)
+#define   C_SQ_ALU_WORD0_INDEX_MODE                                  0xE3FFFFFF
+#define   S_SQ_ALU_WORD0_PRED_SEL(x)                                 (((x) & 0x3) << 29)
+#define   G_SQ_ALU_WORD0_PRED_SEL(x)                                 (((x) >> 29) & 0x3)
+#define   C_SQ_ALU_WORD0_PRED_SEL                                    0x9FFFFFFF
+#define   S_SQ_ALU_WORD0_LAST(x)                                     (((x) & 0x1) << 31)
+#define   G_SQ_ALU_WORD0_LAST(x)                                     (((x) >> 31) & 0x1)
+#define   C_SQ_ALU_WORD0_LAST                                        0x7FFFFFFF
+/* same */
+#define P_SQ_ALU_WORD1
+#define   S_SQ_ALU_WORD1_ENCODING(x)                                 (((x) & 0x7) << 15)
+#define   G_SQ_ALU_WORD1_ENCODING(x)                                 (((x) >> 15) & 0x7)
+#define   C_SQ_ALU_WORD1_ENCODING                                    0xFFFC7FFF
+#define   S_SQ_ALU_WORD1_BANK_SWIZZLE(x)                             (((x) & 0x7) << 18)
+#define   G_SQ_ALU_WORD1_BANK_SWIZZLE(x)                             (((x) >> 18) & 0x7)
+#define   C_SQ_ALU_WORD1_BANK_SWIZZLE                                0xFFE3FFFF
+#define   S_SQ_ALU_WORD1_DST_GPR(x)                                  (((x) & 0x7F) << 21)
+#define   G_SQ_ALU_WORD1_DST_GPR(x)                                  (((x) >> 21) & 0x7F)
+#define   C_SQ_ALU_WORD1_DST_GPR                                     0xF01FFFFF
+#define   S_SQ_ALU_WORD1_DST_REL(x)                                  (((x) & 0x1) << 28)
+#define   G_SQ_ALU_WORD1_DST_REL(x)                                  (((x) >> 28) & 0x1)
+#define   C_SQ_ALU_WORD1_DST_REL                                     0xEFFFFFFF
+#define   S_SQ_ALU_WORD1_DST_CHAN(x)                                 (((x) & 0x3) << 29)
+#define   G_SQ_ALU_WORD1_DST_CHAN(x)                                 (((x) >> 29) & 0x3)
+#define   C_SQ_ALU_WORD1_DST_CHAN                                    0x9FFFFFFF
+#define   S_SQ_ALU_WORD1_CLAMP(x)                                    (((x) & 0x1) << 31)
+#define   G_SQ_ALU_WORD1_CLAMP(x)                                    (((x) >> 31) & 0x1)
+#define   C_SQ_ALU_WORD1_CLAMP                                       0x7FFFFFFF
+/* same except maybe encoding */
+#define P_SQ_ALU_WORD1_OP2
+#define   S_SQ_ALU_WORD1_OP2_SRC0_ABS(x)                             (((x) & 0x1) << 0)
+#define   G_SQ_ALU_WORD1_OP2_SRC0_ABS(x)                             (((x) >> 0) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_SRC0_ABS                                0xFFFFFFFE
+#define   S_SQ_ALU_WORD1_OP2_SRC1_ABS(x)                             (((x) & 0x1) << 1)
+#define   G_SQ_ALU_WORD1_OP2_SRC1_ABS(x)                             (((x) >> 1) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_SRC1_ABS                                0xFFFFFFFD
+#define   S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x)                  (((x) & 0x1) << 2)
+#define   G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(x)                  (((x) >> 2) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK                     0xFFFFFFFB
+#define   S_SQ_ALU_WORD1_OP2_UPDATE_PRED(x)                          (((x) & 0x1) << 3)
+#define   G_SQ_ALU_WORD1_OP2_UPDATE_PRED(x)                          (((x) >> 3) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_UPDATE_PRED                             0xFFFFFFF7
+#define   S_SQ_ALU_WORD1_OP2_WRITE_MASK(x)                           (((x) & 0x1) << 4)
+#define   G_SQ_ALU_WORD1_OP2_WRITE_MASK(x)                           (((x) >> 4) & 0x1)
+#define   C_SQ_ALU_WORD1_OP2_WRITE_MASK                              0xFFFFFFEF
+#define   S_SQ_ALU_WORD1_OP2_OMOD(x)                                 (((x) & 0x3) << 5)
+#define   G_SQ_ALU_WORD1_OP2_OMOD(x)                                 (((x) >> 5) & 0x3)
+#define   C_SQ_ALU_WORD1_OP2_OMOD                                    0xFFFFFF9F
+#define   S_SQ_ALU_WORD1_OP2_ALU_INST(x)                             (((x) & 0x7FF) << 7)
+#define   G_SQ_ALU_WORD1_OP2_ALU_INST(x)                             (((x) >> 7) & 0x7FF)
+#define   C_SQ_ALU_WORD1_OP2_ALU_INST                                0xFFFC007F
+
+#define P_SQ_ALU_WORD1_OP3
+#define   S_SQ_ALU_WORD1_OP3_SRC2_SEL(x)                             (((x) & 0x1FF) << 0)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_SEL(x)                             (((x) >> 0) & 0x1FF)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_SEL                                0xFFFFFE00
+#define   S_SQ_ALU_WORD1_OP3_SRC2_REL(x)                             (((x) & 0x1) << 9)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_REL(x)                             (((x) >> 9) & 0x1)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_REL                                0xFFFFFDFF
+#define   S_SQ_ALU_WORD1_OP3_SRC2_CHAN(x)                            (((x) & 0x3) << 10)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_CHAN(x)                            (((x) >> 10) & 0x3)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_CHAN                               0xFFFFF3FF
+#define   S_SQ_ALU_WORD1_OP3_SRC2_NEG(x)                             (((x) & 0x1) << 12)
+#define   G_SQ_ALU_WORD1_OP3_SRC2_NEG(x)                             (((x) >> 12) & 0x1)
+#define   C_SQ_ALU_WORD1_OP3_SRC2_NEG                                0xFFFFEFFF
+#define   S_SQ_ALU_WORD1_OP3_ALU_INST(x)                             (((x) & 0x1F) << 13)
+#define   G_SQ_ALU_WORD1_OP3_ALU_INST(x)                             (((x) >> 13) & 0x1F)
+#define   C_SQ_ALU_WORD1_OP3_ALU_INST                                0xFFFC1FFF
+/* TODO ADD OTHER OP3 */
+/* done */
+#define P_SQ_VTX_WORD0
+#define   S_SQ_VTX_WORD0_VTX_INST(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_VTX_WORD0_VTX_INST(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_VTX_WORD0_VTX_INST                                    0xFFFFFFE0
+#define   S_SQ_VTX_WORD0_FETCH_TYPE(x)                               (((x) & 0x3) << 5)
+#define   G_SQ_VTX_WORD0_FETCH_TYPE(x)                               (((x) >> 5) & 0x3)
+#define   C_SQ_VTX_WORD0_FETCH_TYPE                                  0xFFFFFF9F
+#define   S_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) & 0x1) << 7)
+#define   G_SQ_VTX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) >> 7) & 0x1)
+#define   C_SQ_VTX_WORD0_FETCH_WHOLE_QUAD                            0xFFFFFF7F
+#define   S_SQ_VTX_WORD0_BUFFER_ID(x)                                (((x) & 0xFF) << 8)
+#define   G_SQ_VTX_WORD0_BUFFER_ID(x)                                (((x) >> 8) & 0xFF)
+#define   C_SQ_VTX_WORD0_BUFFER_ID                                   0xFFFF00FF
+#define   S_SQ_VTX_WORD0_SRC_GPR(x)                                  (((x) & 0x7F) << 16)
+#define   G_SQ_VTX_WORD0_SRC_GPR(x)                                  (((x) >> 16) & 0x7F)
+#define   C_SQ_VTX_WORD0_SRC_GPR                                     0xFF80FFFF
+#define   S_SQ_VTX_WORD0_SRC_REL(x)                                  (((x) & 0x1) << 23)
+#define   G_SQ_VTX_WORD0_SRC_REL(x)                                  (((x) >> 23) & 0x1)
+#define   C_SQ_VTX_WORD0_SRC_REL                                     0xFF7FFFFF
+#define   S_SQ_VTX_WORD0_SRC_SEL_X(x)                                (((x) & 0x3) << 24)
+#define   G_SQ_VTX_WORD0_SRC_SEL_X(x)                                (((x) >> 24) & 0x3)
+#define   C_SQ_VTX_WORD0_SRC_SEL_X                                   0xFCFFFFFF
+#define   S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x)                         (((x) & 0x3F) << 26)
+#define   G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(x)                         (((x) >> 26) & 0x3F)
+#define   C_SQ_VTX_WORD0_MEGA_FETCH_COUNT                            0x03FFFFFF
+/* same WORD 0 */
+#define P_SQ_VTX_WORD1
+#define   S_SQ_VTX_WORD1_DST_SEL_X(x)                                (((x) & 0x7) << 9)
+#define   G_SQ_VTX_WORD1_DST_SEL_X(x)                                (((x) >> 9) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_X                                   0xFFFFF1FF
+#define   S_SQ_VTX_WORD1_DST_SEL_Y(x)                                (((x) & 0x7) << 12)
+#define   G_SQ_VTX_WORD1_DST_SEL_Y(x)                                (((x) >> 12) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_Y                                   0xFFFF8FFF
+#define   S_SQ_VTX_WORD1_DST_SEL_Z(x)                                (((x) & 0x7) << 15)
+#define   G_SQ_VTX_WORD1_DST_SEL_Z(x)                                (((x) >> 15) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_Z                                   0xFFFC7FFF
+#define   S_SQ_VTX_WORD1_DST_SEL_W(x)                                (((x) & 0x7) << 18)
+#define   G_SQ_VTX_WORD1_DST_SEL_W(x)                                (((x) >> 18) & 0x7)
+#define   C_SQ_VTX_WORD1_DST_SEL_W                                   0xFFE3FFFF
+#define   S_SQ_VTX_WORD1_USE_CONST_FIELDS(x)                         (((x) & 0x1) << 21)
+#define   G_SQ_VTX_WORD1_USE_CONST_FIELDS(x)                         (((x) >> 21) & 0x1)
+#define   C_SQ_VTX_WORD1_USE_CONST_FIELDS                            0xFFDFFFFF
+#define   S_SQ_VTX_WORD1_DATA_FORMAT(x)                              (((x) & 0x3F) << 22)
+#define   G_SQ_VTX_WORD1_DATA_FORMAT(x)                              (((x) >> 22) & 0x3F)
+#define   C_SQ_VTX_WORD1_DATA_FORMAT                                 0xF03FFFFF
+#define   S_SQ_VTX_WORD1_NUM_FORMAT_ALL(x)                           (((x) & 0x3) << 28)
+#define   G_SQ_VTX_WORD1_NUM_FORMAT_ALL(x)                           (((x) >> 28) & 0x3)
+#define   C_SQ_VTX_WORD1_NUM_FORMAT_ALL                              0xCFFFFFFF
+#define   S_SQ_VTX_WORD1_FORMAT_COMP_ALL(x)                          (((x) & 0x1) << 30)
+#define   G_SQ_VTX_WORD1_FORMAT_COMP_ALL(x)                          (((x) >> 30) & 0x1)
+#define   C_SQ_VTX_WORD1_FORMAT_COMP_ALL                             0xBFFFFFFF
+#define   S_SQ_VTX_WORD1_SRF_MODE_ALL(x)                             (((x) & 0x1) << 31)
+#define   G_SQ_VTX_WORD1_SRF_MODE_ALL(x)                             (((x) >> 31) & 0x1)
+#define   C_SQ_VTX_WORD1_SRF_MODE_ALL                                0x7FFFFFFF
+/* same WORD1 generic */
+#define P_SQ_VTX_WORD1_GPR
+#define   S_SQ_VTX_WORD1_GPR_DST_GPR(x)                              (((x) & 0x7F) << 0)
+#define   G_SQ_VTX_WORD1_GPR_DST_GPR(x)                              (((x) >> 0) & 0x7F)
+#define   C_SQ_VTX_WORD1_GPR_DST_GPR                                 0xFFFFFF80
+#define   S_SQ_VTX_WORD1_GPR_DST_REL(x)                              (((x) & 0x1) << 7)
+#define   G_SQ_VTX_WORD1_GPR_DST_REL(x)                              (((x) >> 7) & 0x1)
+#define   C_SQ_VTX_WORD1_GPR_DST_REL                                 0xFFFFFF7F
+#define P_SQ_VTX_WORD1_SEM
+#define   S_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x)                          (((x) & 0xFF) << 0)
+#define   G_SQ_VTX_WORD1_SEM_SEMANTIC_ID(x)                          (((x) >> 0) & 0xFF)
+#define   C_SQ_VTX_WORD1_SEM_SEMANTIC_ID                             0xFFFFFF00
+#define P_SQ_VTX_WORD2
+#define   S_SQ_VTX_WORD2_OFFSET(x)                                   (((x) & 0xFFFF) << 0)
+#define   G_SQ_VTX_WORD2_OFFSET(x)                                   (((x) >> 0) & 0xFFFF)
+#define   C_SQ_VTX_WORD2_OFFSET                                      0xFFFF0000
+#define   S_SQ_VTX_WORD2_ENDIAN_SWAP(x)                              (((x) & 0x3) << 16)
+#define   G_SQ_VTX_WORD2_ENDIAN_SWAP(x)                              (((x) >> 16) & 0x3)
+#define   C_SQ_VTX_WORD2_ENDIAN_SWAP                                 0xFFFCFFFF
+#define   S_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x)                      (((x) & 0x1) << 18)
+#define   G_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE(x)                      (((x) >> 18) & 0x1)
+#define   C_SQ_VTX_WORD2_CONST_BUF_NO_STRIDE                         0xFFFBFFFF
+#define   S_SQ_VTX_WORD2_MEGA_FETCH(x)                               (((x) & 0x1) << 19)
+#define   G_SQ_VTX_WORD2_MEGA_FETCH(x)                               (((x) >> 19) & 0x1)
+#define   C_SQ_VTX_WORD2_MEGA_FETCH                                  0xFFF7FFFF
+#define   S_SQ_VTX_WORD2_ALT_CONST(x)                                (((x) & 0x1) << 20)
+#define   G_SQ_VTX_WORD2_ALT_CONST(x)                                (((x) >> 20) & 0x1)
+#define   C_SQ_VTX_WORD2_ALT_CONST                                   0xFFEFFFFF
+#define   S_SQ_VTX_WORD2_BIM(x)                                      (((x) & 0x3) << 21)
+#define   G_SQ_VTX_WORD2_BIM(x)                                      (((x) >> 21) & 0x3)
+#define   C_SQ_VTX_WORD2_BIM                                         0xFF9FFFFF
+/* done */
+
+#define P_SQ_TEX_WORD0
+#define   S_SQ_TEX_WORD0_TEX_INST(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_TEX_WORD0_TEX_INST(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_TEX_WORD0_TEX_INST                                    0xFFFFFFE0
+#define   S_SQ_TEX_WORD0_INST_MOD(x)                                 (((x) & 0x3) << 5)
+#define   G_SQ_TEX_WORD0_INST_MOD(x)                                 (((x) >> 5) & 0x3)
+#define   C_SQ_TEX_WORD0_INST_MOD                                    0xFFFFFF9F
+#define   S_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) & 0x1) << 7)
+#define   G_SQ_TEX_WORD0_FETCH_WHOLE_QUAD(x)                         (((x) >> 7) & 0x1)
+#define   C_SQ_TEX_WORD0_FETCH_WHOLE_QUAD                            0xFFFFFF7F
+#define   S_SQ_TEX_WORD0_RESOURCE_ID(x)                              (((x) & 0xFF) << 8)
+#define   G_SQ_TEX_WORD0_RESOURCE_ID(x)                              (((x) >> 8) & 0xFF)
+#define   C_SQ_TEX_WORD0_RESOURCE_ID                                 0xFFFF00FF
+#define   S_SQ_TEX_WORD0_SRC_GPR(x)                                  (((x) & 0x7F) << 16)
+#define   G_SQ_TEX_WORD0_SRC_GPR(x)                                  (((x) >> 16) & 0x7F)
+#define   C_SQ_TEX_WORD0_SRC_GPR                                     0xFF80FFFF
+#define   S_SQ_TEX_WORD0_SRC_REL(x)                                  (((x) & 0x1) << 23)
+#define   G_SQ_TEX_WORD0_SRC_REL(x)                                  (((x) >> 23) & 0x1)
+#define   C_SQ_TEX_WORD0_SRC_REL                                     0xFF7FFFFF
+#define   S_SQ_TEX_WORD0_ALT_CONST(x)                                (((x) & 0x1) << 24)
+#define   G_SQ_TEX_WORD0_ALT_CONST(x)                                (((x) >> 24) & 0x1)
+#define   C_SQ_TEX_WORD0_ALT_CONST                                   0xFEFFFFFF
+#define   S_SQ_TEX_WORD0_RIM(x)                                      (((x) & 0x3) << 25)
+#define   G_SQ_TEX_WORD0_RIM(x)                                      (((x) >> 25) & 0x3)
+#define   C_SQ_TEX_WORD0_RIM                                         0xF9FFFFFF
+#define   S_SQ_TEX_WORD0_SIM(x)                                      (((x) & 0x3) << 27)
+#define   G_SQ_TEX_WORD0_SIM(x)                                      (((x) >> 27) & 0x3)
+#define   C_SQ_TEX_WORD0_SIM                                         0xE7FFFFFF
+#define P_SQ_TEX_WORD1
+#define   S_SQ_TEX_WORD1_DST_GPR(x)                                  (((x) & 0x7F) << 0)
+#define   G_SQ_TEX_WORD1_DST_GPR(x)                                  (((x) >> 0) & 0x7F)
+#define   C_SQ_TEX_WORD1_DST_GPR                                     0xFFFFFF80
+#define   S_SQ_TEX_WORD1_DST_REL(x)                                  (((x) & 0x1) << 7)
+#define   G_SQ_TEX_WORD1_DST_REL(x)                                  (((x) >> 7) & 0x1)
+#define   C_SQ_TEX_WORD1_DST_REL                                     0xFFFFFF7F
+#define   S_SQ_TEX_WORD1_DST_SEL_X(x)                                (((x) & 0x7) << 9)
+#define   G_SQ_TEX_WORD1_DST_SEL_X(x)                                (((x) >> 9) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_X                                   0xFFFFF1FF
+#define   S_SQ_TEX_WORD1_DST_SEL_Y(x)                                (((x) & 0x7) << 12)
+#define   G_SQ_TEX_WORD1_DST_SEL_Y(x)                                (((x) >> 12) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_Y                                   0xFFFF8FFF
+#define   S_SQ_TEX_WORD1_DST_SEL_Z(x)                                (((x) & 0x7) << 15)
+#define   G_SQ_TEX_WORD1_DST_SEL_Z(x)                                (((x) >> 15) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_Z                                   0xFFFC7FFF
+#define   S_SQ_TEX_WORD1_DST_SEL_W(x)                                (((x) & 0x7) << 18)
+#define   G_SQ_TEX_WORD1_DST_SEL_W(x)                                (((x) >> 18) & 0x7)
+#define   C_SQ_TEX_WORD1_DST_SEL_W                                   0xFFE3FFFF
+#define   S_SQ_TEX_WORD1_LOD_BIAS(x)                                 (((x) & 0x7F) << 21)
+#define   G_SQ_TEX_WORD1_LOD_BIAS(x)                                 (((x) >> 21) & 0x7F)
+#define   C_SQ_TEX_WORD1_LOD_BIAS                                    0xF01FFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_X(x)                             (((x) & 0x1) << 28)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_X(x)                             (((x) >> 28) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_X                                0xEFFFFFFF
+#define     V_SQ_TEX_WORD1_COORD_UNNORMALIZED                        0x00000000
+#define     V_SQ_TEX_WORD1_COORD_NORMALIZED                          0x00000001
+#define   S_SQ_TEX_WORD1_COORD_TYPE_Y(x)                             (((x) & 0x1) << 29)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_Y(x)                             (((x) >> 29) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_Y                                0xDFFFFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_Z(x)                             (((x) & 0x1) << 30)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_Z(x)                             (((x) >> 30) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_Z                                0xBFFFFFFF
+#define   S_SQ_TEX_WORD1_COORD_TYPE_W(x)                             (((x) & 0x1) << 31)
+#define   G_SQ_TEX_WORD1_COORD_TYPE_W(x)                             (((x) >> 31) & 0x1)
+#define   C_SQ_TEX_WORD1_COORD_TYPE_W                                0x7FFFFFFF
+#define P_SQ_TEX_WORD2
+#define   S_SQ_TEX_WORD2_OFFSET_X(x)                                 (((x) & 0x1F) << 0)
+#define   G_SQ_TEX_WORD2_OFFSET_X(x)                                 (((x) >> 0) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_X                                    0xFFFFFFE0
+#define   S_SQ_TEX_WORD2_OFFSET_Y(x)                                 (((x) & 0x1F) << 5)
+#define   G_SQ_TEX_WORD2_OFFSET_Y(x)                                 (((x) >> 5) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_Y                                    0xFFFFFC1F
+#define   S_SQ_TEX_WORD2_OFFSET_Z(x)                                 (((x) & 0x1F) << 10)
+#define   G_SQ_TEX_WORD2_OFFSET_Z(x)                                 (((x) >> 10) & 0x1F)
+#define   C_SQ_TEX_WORD2_OFFSET_Z                                    0xFFFF83FF
+#define   S_SQ_TEX_WORD2_SAMPLER_ID(x)                               (((x) & 0x1F) << 15)
+#define   G_SQ_TEX_WORD2_SAMPLER_ID(x)                               (((x) >> 15) & 0x1F)
+#define   C_SQ_TEX_WORD2_SAMPLER_ID                                  0xFFF07FFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_X(x)                                (((x) & 0x7) << 20)
+#define   G_SQ_TEX_WORD2_SRC_SEL_X(x)                                (((x) >> 20) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_X                                   0xFF8FFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_Y(x)                                (((x) & 0x7) << 23)
+#define   G_SQ_TEX_WORD2_SRC_SEL_Y(x)                                (((x) >> 23) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_Y                                   0xFC7FFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_Z(x)                                (((x) & 0x7) << 26)
+#define   G_SQ_TEX_WORD2_SRC_SEL_Z(x)                                (((x) >> 26) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_Z                                   0xE3FFFFFF
+#define   S_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) & 0x7) << 29)
+#define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
+#define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
+
+#define V_SQ_CF_COND_ACTIVE                             0x00
+#define V_SQ_CF_COND_FALSE                              0x01
+#define V_SQ_CF_COND_BOOL                               0x02
+#define V_SQ_CF_COND_NOT_BOOL                           0x03
+
+#define V_SQ_REL_ABSOLUTE 0
+#define V_SQ_REL_RELATIVE 1
+#endif
diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h
new file mode 100644
index 00000000000..4e3514638b7
--- /dev/null
+++ b/src/gallium/drivers/r600/eg_state_inlines.h
@@ -0,0 +1,434 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef EG_STATE_INLINES_H
+#define EG_STATE_INLINES_H
+
+#include "util/u_format.h"
+#include "evergreend.h"
+
+static INLINE uint32_t r600_translate_blend_function(int blend_func)
+{
+	switch (blend_func) {
+	case PIPE_BLEND_ADD:
+		return V_028780_COMB_DST_PLUS_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return V_028780_COMB_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return V_028780_COMB_DST_MINUS_SRC;
+	case PIPE_BLEND_MIN:
+		return V_028780_COMB_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return V_028780_COMB_MAX_DST_SRC;
+	default:
+		R600_ERR("Unknown blend function %d\n", blend_func);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
+{
+	switch (blend_fact) {
+	case PIPE_BLENDFACTOR_ONE:
+		return V_028780_BLEND_ONE;
+	case PIPE_BLENDFACTOR_SRC_COLOR:
+		return V_028780_BLEND_SRC_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return V_028780_BLEND_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_DST_ALPHA:
+		return V_028780_BLEND_DST_ALPHA;
+	case PIPE_BLENDFACTOR_DST_COLOR:
+		return V_028780_BLEND_DST_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return V_028780_BLEND_SRC_ALPHA_SATURATE;
+	case PIPE_BLENDFACTOR_CONST_COLOR:
+		return V_028780_BLEND_CONST_COLOR;
+	case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return V_028780_BLEND_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_ZERO:
+		return V_028780_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return V_028780_BLEND_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return V_028780_BLEND_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return V_028780_BLEND_INV_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return V_028780_BLEND_INV_SRC1_ALPHA;
+	default:
+		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static INLINE uint32_t r600_translate_stencil_op(int s_op)
+{
+	switch (s_op) {
+	case PIPE_STENCIL_OP_KEEP:
+		return V_028800_STENCIL_KEEP;
+	case PIPE_STENCIL_OP_ZERO:
+		return V_028800_STENCIL_ZERO;
+	case PIPE_STENCIL_OP_REPLACE:
+		return V_028800_STENCIL_REPLACE;
+	case PIPE_STENCIL_OP_INCR:
+		return V_028800_STENCIL_INCR;
+	case PIPE_STENCIL_OP_DECR:
+		return V_028800_STENCIL_DECR;
+	case PIPE_STENCIL_OP_INCR_WRAP:
+		return V_028800_STENCIL_INCR_WRAP;
+	case PIPE_STENCIL_OP_DECR_WRAP:
+		return V_028800_STENCIL_DECR_WRAP;
+	case PIPE_STENCIL_OP_INVERT:
+		return V_028800_STENCIL_INVERT;
+	default:
+		R600_ERR("Unknown stencil op %d", s_op);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+/* translates straight */
+static INLINE uint32_t r600_translate_ds_func(int func)
+{
+	return func;
+}
+
+static inline unsigned r600_tex_wrap(unsigned wrap)
+{
+	switch (wrap) {
+	default:
+	case PIPE_TEX_WRAP_REPEAT:
+		return V_03C000_SQ_TEX_WRAP;
+	case PIPE_TEX_WRAP_CLAMP:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_CLAMP_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_REPEAT:
+		return V_03C000_SQ_TEX_MIRROR;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+	}
+}
+
+static inline unsigned r600_tex_filter(unsigned filter)
+{
+	switch (filter) {
+	default:
+	case PIPE_TEX_FILTER_NEAREST:
+		return V_03C000_SQ_TEX_XY_FILTER_POINT;
+	case PIPE_TEX_FILTER_LINEAR:
+		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+	}
+}
+
+static inline unsigned r600_tex_mipfilter(unsigned filter)
+{
+	switch (filter) {
+	case PIPE_TEX_MIPFILTER_NEAREST:
+		return V_03C000_SQ_TEX_Z_FILTER_POINT;
+	case PIPE_TEX_MIPFILTER_LINEAR:
+		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+	default:
+	case PIPE_TEX_MIPFILTER_NONE:
+		return V_03C000_SQ_TEX_Z_FILTER_NONE;
+	}
+}
+
+static inline unsigned r600_tex_compare(unsigned compare)
+{
+	switch (compare) {
+	default:
+	case PIPE_FUNC_NEVER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+	case PIPE_FUNC_LESS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+	case PIPE_FUNC_EQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+	case PIPE_FUNC_GREATER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+	case PIPE_FUNC_NOTEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+	}
+}
+
+static inline unsigned r600_tex_swizzle(unsigned swizzle)
+{
+	switch (swizzle) {
+	case PIPE_SWIZZLE_RED:
+		return V_030010_SQ_SEL_X;
+	case PIPE_SWIZZLE_GREEN:
+		return V_030010_SQ_SEL_Y;
+	case PIPE_SWIZZLE_BLUE:
+		return V_030010_SQ_SEL_Z;
+	case PIPE_SWIZZLE_ALPHA:
+		return V_030010_SQ_SEL_W;
+	case PIPE_SWIZZLE_ZERO:
+		return V_030010_SQ_SEL_0;
+	default:
+	case PIPE_SWIZZLE_ONE:
+		return V_030010_SQ_SEL_1;
+	}
+}
+
+static inline unsigned r600_format_type(unsigned format_type)
+{
+	switch (format_type) {
+	default:
+	case UTIL_FORMAT_TYPE_UNSIGNED:
+		return V_030010_SQ_FORMAT_COMP_UNSIGNED;
+	case UTIL_FORMAT_TYPE_SIGNED:
+		return V_030010_SQ_FORMAT_COMP_SIGNED;
+	case UTIL_FORMAT_TYPE_FIXED:
+		return V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
+	}
+}
+
+static inline unsigned r600_tex_dim(unsigned dim)
+{
+	switch (dim) {
+	default:
+	case PIPE_TEXTURE_1D:
+		return V_030000_SQ_TEX_DIM_1D;
+	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
+		return V_030000_SQ_TEX_DIM_2D;
+	case PIPE_TEXTURE_3D:
+		return V_030000_SQ_TEX_DIM_3D;
+	case PIPE_TEXTURE_CUBE:
+		return V_030000_SQ_TEX_DIM_CUBEMAP;
+	}
+}
+
+static inline uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028040_Z_16;
+	case PIPE_FORMAT_Z24X8_UNORM:
+		return V_028040_Z_24;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028040_Z_24;
+	default:
+		return ~0;
+	}
+}
+
+static inline uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_028C70_SWAP_STD;
+
+		/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_028C70_SWAP_STD_REV;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_028C70_SWAP_ALT;
+		/* 32-bit buffers. */
+
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return V_028C70_SWAP_STD_REV;
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_028C70_SWAP_ALT_REV;
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+		//        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+		return V_028C70_SWAP_STD_REV;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_028C70_SWAP_STD_REV;
+
+		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		//		return V_028C70_COLOR_16_16_16_16;
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		//		return V_028C70_COLOR_16_16_16_16_FLOAT;
+
+		/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		//		return V_028C70_COLOR_32_32_32_32_FLOAT;
+		return 0;
+	default:
+		R600_ERR("unsupported colorswap format %d\n", format);
+		return ~0;
+	}
+	return ~0;
+}
+
+static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_028C70_COLOR_8;
+
+		/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_028C70_COLOR_5_6_5;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_028C70_COLOR_1_5_5_5;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_028C70_COLOR_4_4_4_4;
+
+		/* 32-bit buffers. */
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_R8G8B8_UNORM:
+		return V_028C70_COLOR_8_8_8_8;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_028C70_COLOR_10_10_10_2;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028C70_COLOR_8_24;
+
+	case PIPE_FORMAT_R32_FLOAT:
+		return V_028C70_COLOR_32_FLOAT;
+
+		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		return V_028C70_COLOR_16_16_16_16;
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		return V_028C70_COLOR_16_16_16_16_FLOAT;
+	case PIPE_FORMAT_R32G32_FLOAT:
+		return V_028C70_COLOR_32_32_FLOAT;
+
+		/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32_FLOAT:
+	  	return V_028C70_COLOR_32_32_32_FLOAT;
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		return V_028C70_COLOR_32_32_32_32_FLOAT;
+
+		/* YUV buffers. */
+	case PIPE_FORMAT_UYVY:
+	case PIPE_FORMAT_YUYV:
+	default:
+		R600_ERR("unsupported color format %d\n", format);
+		return ~0; /* Unsupported. */
+	}
+}
+
+static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
+{
+	return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
+}
+
+static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0 &&
+		r600_translate_colorswap(format) != ~0;
+}
+
+static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
+{
+	return r600_translate_dbformat(format) != ~0;
+}
+
+static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0;
+}
+
+#endif
diff --git a/src/gallium/drivers/r600/eg_states_inc.h b/src/gallium/drivers/r600/eg_states_inc.h
new file mode 100644
index 00000000000..ebfc36cbca0
--- /dev/null
+++ b/src/gallium/drivers/r600/eg_states_inc.h
@@ -0,0 +1,521 @@
+/* This file is autogenerated from eg_states.h - do not edit directly */
+/* autogenerating script is gen_eg_states.py */
+
+/* EG_CONFIG */
+#define EG_CONFIG__SQ_CONFIG		0
+#define EG_CONFIG__SPI_CONFIG_CNTL		1
+#define EG_CONFIG__SPI_CONFIG_CNTL_1		2
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1		3
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2		4
+#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3		5
+#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1		6
+#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2		7
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1		8
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2		9
+#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3		10
+#define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ		11
+#define EG_CONFIG__PA_CL_ENHANCE		12
+#define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1		13
+#define EG_CONFIG__SQ_LDS_ALLOC_PS		14
+#define EG_CONFIG__SX_MISC		15
+#define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE		16
+#define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE		17
+#define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE		18
+#define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE		19
+#define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE		20
+#define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE		21
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE		22
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1		23
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2		24
+#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3		25
+#define EG_CONFIG__VGT_OUTPUT_PATH_CNTL		26
+#define EG_CONFIG__VGT_HOS_CNTL		27
+#define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL		28
+#define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL		29
+#define EG_CONFIG__VGT_HOS_REUSE_DEPTH		30
+#define EG_CONFIG__VGT_GROUP_PRIM_TYPE		31
+#define EG_CONFIG__VGT_GROUP_FIRST_DECR		32
+#define EG_CONFIG__VGT_GROUP_DECR		33
+#define EG_CONFIG__VGT_GROUP_VECT_0_CNTL		34
+#define EG_CONFIG__VGT_GROUP_VECT_1_CNTL		35
+#define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL		36
+#define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL		37
+#define EG_CONFIG__VGT_GS_MODE		38
+#define EG_CONFIG__PA_SC_MODE_CNTL_0		39
+#define EG_CONFIG__PA_SC_MODE_CNTL_1		40
+#define EG_CONFIG__VGT_REUSE_OFF		41
+#define EG_CONFIG__VGT_VTX_CNT_EN		42
+#define EG_CONFIG__VGT_SHADER_STAGES_EN		43
+#define EG_CONFIG__VGT_STRMOUT_CONFIG		44
+#define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG		45
+#define EG_CONFIG_SIZE		46
+#define EG_CONFIG_PM4 128		
+
+/* EG_CB_CNTL */
+#define EG_CB_CNTL__CB_TARGET_MASK		0
+#define EG_CB_CNTL__CB_SHADER_MASK		1
+#define EG_CB_CNTL__CB_COLOR_CONTROL		2
+#define EG_CB_CNTL__PA_SC_AA_CONFIG		3
+#define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX		4
+#define EG_CB_CNTL__PA_SC_AA_MASK		5
+#define EG_CB_CNTL_SIZE		6
+#define EG_CB_CNTL_PM4 128		
+
+/* EG_RASTERIZER */
+#define EG_RASTERIZER__SPI_INTERP_CONTROL_0		0
+#define EG_RASTERIZER__PA_CL_CLIP_CNTL		1
+#define EG_RASTERIZER__PA_SU_SC_MODE_CNTL		2
+#define EG_RASTERIZER__PA_CL_VS_OUT_CNTL		3
+#define EG_RASTERIZER__PA_CL_NANINF_CNTL		4
+#define EG_RASTERIZER__PA_SU_POINT_SIZE		5
+#define EG_RASTERIZER__PA_SU_POINT_MINMAX		6
+#define EG_RASTERIZER__PA_SU_LINE_CNTL		7
+#define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL		8
+#define EG_RASTERIZER__PA_SC_LINE_CNTL		9
+#define EG_RASTERIZER__PA_SU_VTX_CNTL		10
+#define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ		11
+#define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ		12
+#define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ		13
+#define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ		14
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL		15
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP		16
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE		17
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET		18
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE		19
+#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET		20
+#define EG_RASTERIZER_SIZE		21
+#define EG_RASTERIZER_PM4 128		
+
+/* EG_VIEWPORT */
+#define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0		0
+#define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0		1
+#define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0		2
+#define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0		3
+#define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0		4
+#define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0		5
+#define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0		6
+#define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0		7
+#define EG_VIEWPORT__PA_CL_VTE_CNTL		8
+#define EG_VIEWPORT_SIZE		9
+#define EG_VIEWPORT_PM4 128		
+
+/* EG_SCISSOR */
+#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL		0
+#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR		1
+#define EG_SCISSOR__PA_SC_WINDOW_OFFSET		2
+#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL		3
+#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR		4
+#define EG_SCISSOR__PA_SC_CLIPRECT_RULE		5
+#define EG_SCISSOR__PA_SC_CLIPRECT_0_TL		6
+#define EG_SCISSOR__PA_SC_CLIPRECT_0_BR		7
+#define EG_SCISSOR__PA_SC_CLIPRECT_1_TL		8
+#define EG_SCISSOR__PA_SC_CLIPRECT_1_BR		9
+#define EG_SCISSOR__PA_SC_CLIPRECT_2_TL		10
+#define EG_SCISSOR__PA_SC_CLIPRECT_2_BR		11
+#define EG_SCISSOR__PA_SC_CLIPRECT_3_TL		12
+#define EG_SCISSOR__PA_SC_CLIPRECT_3_BR		13
+#define EG_SCISSOR__PA_SC_EDGERULE		14
+#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL		15
+#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR		16
+#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL		17
+#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR		18
+#define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET		19
+#define EG_SCISSOR_SIZE		20
+#define EG_SCISSOR_PM4 128		
+
+/* EG_BLEND */
+#define EG_BLEND__CB_BLEND_RED		0
+#define EG_BLEND__CB_BLEND_GREEN		1
+#define EG_BLEND__CB_BLEND_BLUE		2
+#define EG_BLEND__CB_BLEND_ALPHA		3
+#define EG_BLEND__CB_BLEND0_CONTROL		4
+#define EG_BLEND__CB_BLEND1_CONTROL		5
+#define EG_BLEND__CB_BLEND2_CONTROL		6
+#define EG_BLEND__CB_BLEND3_CONTROL		7
+#define EG_BLEND__CB_BLEND4_CONTROL		8
+#define EG_BLEND__CB_BLEND5_CONTROL		9
+#define EG_BLEND__CB_BLEND6_CONTROL		10
+#define EG_BLEND__CB_BLEND7_CONTROL		11
+#define EG_BLEND_SIZE		12
+#define EG_BLEND_PM4 128		
+
+/* EG_DSA */
+#define EG_DSA__DB_STENCIL_CLEAR		0
+#define EG_DSA__DB_DEPTH_CLEAR		1
+#define EG_DSA__SX_ALPHA_TEST_CONTROL		2
+#define EG_DSA__DB_STENCILREFMASK		3
+#define EG_DSA__DB_STENCILREFMASK_BF		4
+#define EG_DSA__SX_ALPHA_REF		5
+#define EG_DSA__SPI_FOG_CNTL		6
+#define EG_DSA__DB_DEPTH_CONTROL		7
+#define EG_DSA__DB_SHADER_CONTROL		8
+#define EG_DSA__DB_RENDER_CONTROL		9
+#define EG_DSA__DB_RENDER_OVERRIDE		10
+#define EG_DSA__DB_RENDER_OVERRIDE2		11
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE0		12
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE1		13
+#define EG_DSA__DB_PRELOAD_CONTROL		14
+#define EG_DSA__DB_ALPHA_TO_MASK		15
+#define EG_DSA_SIZE		16
+#define EG_DSA_PM4 128		
+
+/* EG_VS_SHADER */
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_0		0
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_1		1
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_2		2
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_3		3
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_4		4
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_5		5
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_6		6
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_7		7
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_8		8
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_9		9
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_10		10
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_11		11
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_12		12
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_13		13
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_14		14
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_15		15
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_16		16
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_17		17
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_18		18
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_19		19
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_20		20
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_21		21
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_22		22
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_23		23
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_24		24
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_25		25
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_26		26
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_27		27
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_28		28
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_29		29
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_30		30
+#define EG_VS_SHADER__SQ_VTX_SEMANTIC_31		31
+#define EG_VS_SHADER__SPI_VS_OUT_ID_0		32
+#define EG_VS_SHADER__SPI_VS_OUT_ID_1		33
+#define EG_VS_SHADER__SPI_VS_OUT_ID_2		34
+#define EG_VS_SHADER__SPI_VS_OUT_ID_3		35
+#define EG_VS_SHADER__SPI_VS_OUT_ID_4		36
+#define EG_VS_SHADER__SPI_VS_OUT_ID_5		37
+#define EG_VS_SHADER__SPI_VS_OUT_ID_6		38
+#define EG_VS_SHADER__SPI_VS_OUT_ID_7		39
+#define EG_VS_SHADER__SPI_VS_OUT_ID_8		40
+#define EG_VS_SHADER__SPI_VS_OUT_ID_9		41
+#define EG_VS_SHADER__SPI_VS_OUT_CONFIG		42
+#define EG_VS_SHADER__SQ_PGM_START_VS		43
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_VS		44
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS		45
+#define EG_VS_SHADER__SQ_PGM_START_FS		46
+#define EG_VS_SHADER__SQ_PGM_RESOURCES_FS		47
+#define EG_VS_SHADER_SIZE		48
+#define EG_VS_SHADER_PM4 128		
+
+/* EG_PS_SHADER */
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0		0
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1		1
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2		2
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3		3
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4		4
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5		5
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6		6
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7		7
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8		8
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9		9
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10		10
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11		11
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12		12
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13		13
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14		14
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15		15
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16		16
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17		17
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18		18
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19		19
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20		20
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21		21
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22		22
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23		23
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24		24
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25		25
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26		26
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27		27
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28		28
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29		29
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30		30
+#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31		31
+#define EG_PS_SHADER__SPI_THREAD_GROUPING		32
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_0		33
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_1		34
+#define EG_PS_SHADER__SPI_INPUT_Z		35
+#define EG_PS_SHADER__SPI_BARYC_CNTL		36
+#define EG_PS_SHADER__SPI_PS_IN_CONTROL_2		37
+#define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL		38
+#define EG_PS_SHADER__SQ_PGM_START_PS		39
+#define EG_PS_SHADER__SQ_PGM_RESOURCES_PS		40
+#define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS		41
+#define EG_PS_SHADER__SQ_PGM_EXPORTS_PS		42
+#define EG_PS_SHADER_SIZE		43
+#define EG_PS_SHADER_PM4 128		
+
+/* EG_UCP */
+#define EG_UCP__PA_CL_UCP0_X		0
+#define EG_UCP__PA_CL_UCP0_Y		1
+#define EG_UCP__PA_CL_UCP0_Z		2
+#define EG_UCP__PA_CL_UCP0_W		3
+#define EG_UCP__PA_CL_UCP1_X		4
+#define EG_UCP__PA_CL_UCP1_Y		5
+#define EG_UCP__PA_CL_UCP1_Z		6
+#define EG_UCP__PA_CL_UCP1_W		7
+#define EG_UCP__PA_CL_UCP2_X		8
+#define EG_UCP__PA_CL_UCP2_Y		9
+#define EG_UCP__PA_CL_UCP2_Z		10
+#define EG_UCP__PA_CL_UCP2_W		11
+#define EG_UCP__PA_CL_UCP3_X		12
+#define EG_UCP__PA_CL_UCP3_Y		13
+#define EG_UCP__PA_CL_UCP3_Z		14
+#define EG_UCP__PA_CL_UCP3_W		15
+#define EG_UCP__PA_CL_UCP4_X		16
+#define EG_UCP__PA_CL_UCP4_Y		17
+#define EG_UCP__PA_CL_UCP4_Z		18
+#define EG_UCP__PA_CL_UCP4_W		19
+#define EG_UCP__PA_CL_UCP5_X		20
+#define EG_UCP__PA_CL_UCP5_Y		21
+#define EG_UCP__PA_CL_UCP5_Z		22
+#define EG_UCP__PA_CL_UCP5_W		23
+#define EG_UCP_SIZE		24
+#define EG_UCP_PM4 128		
+
+/* EG_VS_CBUF */
+#define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0		0
+#define EG_VS_CBUF__ALU_CONST_CACHE_VS_0		1
+#define EG_VS_CBUF_SIZE		2
+#define EG_VS_CBUF_PM4 128		
+
+/* EG_PS_CBUF */
+#define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0		0
+#define EG_PS_CBUF__ALU_CONST_CACHE_PS_0		1
+#define EG_PS_CBUF_SIZE		2
+#define EG_PS_CBUF_PM4 128		
+
+/* EG_PS_RESOURCE */
+#define EG_PS_RESOURCE__RESOURCE0_WORD0		0
+#define EG_PS_RESOURCE__RESOURCE0_WORD1		1
+#define EG_PS_RESOURCE__RESOURCE0_WORD2		2
+#define EG_PS_RESOURCE__RESOURCE0_WORD3		3
+#define EG_PS_RESOURCE__RESOURCE0_WORD4		4
+#define EG_PS_RESOURCE__RESOURCE0_WORD5		5
+#define EG_PS_RESOURCE__RESOURCE0_WORD6		6
+#define EG_PS_RESOURCE__RESOURCE0_WORD7		7
+#define EG_PS_RESOURCE_SIZE		8
+#define EG_PS_RESOURCE_PM4 128		
+
+/* EG_VS_RESOURCE */
+#define EG_VS_RESOURCE__RESOURCE160_WORD0		0
+#define EG_VS_RESOURCE__RESOURCE160_WORD1		1
+#define EG_VS_RESOURCE__RESOURCE160_WORD2		2
+#define EG_VS_RESOURCE__RESOURCE160_WORD3		3
+#define EG_VS_RESOURCE__RESOURCE160_WORD4		4
+#define EG_VS_RESOURCE__RESOURCE160_WORD5		5
+#define EG_VS_RESOURCE__RESOURCE160_WORD6		6
+#define EG_VS_RESOURCE__RESOURCE160_WORD7		7
+#define EG_VS_RESOURCE_SIZE		8
+#define EG_VS_RESOURCE_PM4 128		
+
+/* EG_FS_RESOURCE */
+#define EG_FS_RESOURCE__RESOURCE320_WORD0		0
+#define EG_FS_RESOURCE__RESOURCE320_WORD1		1
+#define EG_FS_RESOURCE__RESOURCE320_WORD2		2
+#define EG_FS_RESOURCE__RESOURCE320_WORD3		3
+#define EG_FS_RESOURCE__RESOURCE320_WORD4		4
+#define EG_FS_RESOURCE__RESOURCE320_WORD5		5
+#define EG_FS_RESOURCE__RESOURCE320_WORD6		6
+#define EG_FS_RESOURCE_SIZE		7
+#define EG_FS_RESOURCE_PM4 128		
+
+/* EG_GS_RESOURCE */
+#define EG_GS_RESOURCE__RESOURCE336_WORD0		0
+#define EG_GS_RESOURCE__RESOURCE336_WORD1		1
+#define EG_GS_RESOURCE__RESOURCE336_WORD2		2
+#define EG_GS_RESOURCE__RESOURCE336_WORD3		3
+#define EG_GS_RESOURCE__RESOURCE336_WORD4		4
+#define EG_GS_RESOURCE__RESOURCE336_WORD5		5
+#define EG_GS_RESOURCE__RESOURCE336_WORD6		6
+#define EG_GS_RESOURCE_SIZE		7
+#define EG_GS_RESOURCE_PM4 128		
+
+/* EG_PS_SAMPLER */
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0		0
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0		1
+#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0		2
+#define EG_PS_SAMPLER_SIZE		3
+#define EG_PS_SAMPLER_PM4 128		
+
+/* EG_VS_SAMPLER */
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18		0
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18		1
+#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18		2
+#define EG_VS_SAMPLER_SIZE		3
+#define EG_VS_SAMPLER_PM4 128		
+
+/* EG_GS_SAMPLER */
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36		0
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36		1
+#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36		2
+#define EG_GS_SAMPLER_SIZE		3
+#define EG_GS_SAMPLER_PM4 128		
+
+/* EG_PS_SAMPLER_BORDER */
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED		0
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN		1
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE		2
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA		3
+#define EG_PS_SAMPLER_BORDER_SIZE		4
+#define EG_PS_SAMPLER_BORDER_PM4 128		
+
+/* EG_VS_SAMPLER_BORDER */
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED		0
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN		1
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE		2
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA		3
+#define EG_VS_SAMPLER_BORDER_SIZE		4
+#define EG_VS_SAMPLER_BORDER_PM4 128		
+
+/* EG_GS_SAMPLER_BORDER */
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED		0
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN		1
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE		2
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA		3
+#define EG_GS_SAMPLER_BORDER_SIZE		4
+#define EG_GS_SAMPLER_BORDER_PM4 128		
+
+/* EG_CB0 */
+#define EG_CB0__CB_COLOR0_BASE		0
+#define EG_CB0__CB_COLOR0_PITCH		1
+#define EG_CB0__CB_COLOR0_SLICE		2
+#define EG_CB0__CB_COLOR0_VIEW		3
+#define EG_CB0__CB_COLOR0_INFO		4
+#define EG_CB0__CB_COLOR0_ATTRIB		5
+#define EG_CB0__CB_COLOR0_DIM		6
+#define EG_CB0_SIZE		7
+#define EG_CB0_PM4 128		
+
+/* EG_CB1 */
+#define EG_CB1__CB_COLOR1_BASE		0
+#define EG_CB1__CB_COLOR1_INFO		1
+#define EG_CB1__CB_COLOR1_SIZE		2
+#define EG_CB1__CB_COLOR1_VIEW		3
+#define EG_CB1__CB_COLOR1_FRAG		4
+#define EG_CB1__CB_COLOR1_TILE		5
+#define EG_CB1__CB_COLOR1_MASK		6
+#define EG_CB1_SIZE		7
+#define EG_CB1_PM4 128		
+
+/* EG_CB2 */
+#define EG_CB2__CB_COLOR2_BASE		0
+#define EG_CB2__CB_COLOR2_INFO		1
+#define EG_CB2__CB_COLOR2_SIZE		2
+#define EG_CB2__CB_COLOR2_VIEW		3
+#define EG_CB2__CB_COLOR2_FRAG		4
+#define EG_CB2__CB_COLOR2_TILE		5
+#define EG_CB2__CB_COLOR2_MASK		6
+#define EG_CB2_SIZE		7
+#define EG_CB2_PM4 128		
+
+/* EG_CB3 */
+#define EG_CB3__CB_COLOR3_BASE		0
+#define EG_CB3__CB_COLOR3_INFO		1
+#define EG_CB3__CB_COLOR3_SIZE		2
+#define EG_CB3__CB_COLOR3_VIEW		3
+#define EG_CB3__CB_COLOR3_FRAG		4
+#define EG_CB3__CB_COLOR3_TILE		5
+#define EG_CB3__CB_COLOR3_MASK		6
+#define EG_CB3_SIZE		7
+#define EG_CB3_PM4 128		
+
+/* EG_CB4 */
+#define EG_CB4__CB_COLOR4_BASE		0
+#define EG_CB4__CB_COLOR4_INFO		1
+#define EG_CB4__CB_COLOR4_SIZE		2
+#define EG_CB4__CB_COLOR4_VIEW		3
+#define EG_CB4__CB_COLOR4_FRAG		4
+#define EG_CB4__CB_COLOR4_TILE		5
+#define EG_CB4__CB_COLOR4_MASK		6
+#define EG_CB4_SIZE		7
+#define EG_CB4_PM4 128		
+
+/* EG_CB5 */
+#define EG_CB5__CB_COLOR5_BASE		0
+#define EG_CB5__CB_COLOR5_INFO		1
+#define EG_CB5__CB_COLOR5_SIZE		2
+#define EG_CB5__CB_COLOR5_VIEW		3
+#define EG_CB5__CB_COLOR5_FRAG		4
+#define EG_CB5__CB_COLOR5_TILE		5
+#define EG_CB5__CB_COLOR5_MASK		6
+#define EG_CB5_SIZE		7
+#define EG_CB5_PM4 128		
+
+/* EG_CB6 */
+#define EG_CB6__CB_COLOR6_BASE		0
+#define EG_CB6__CB_COLOR6_INFO		1
+#define EG_CB6__CB_COLOR6_SIZE		2
+#define EG_CB6__CB_COLOR6_VIEW		3
+#define EG_CB6__CB_COLOR6_FRAG		4
+#define EG_CB6__CB_COLOR6_TILE		5
+#define EG_CB6__CB_COLOR6_MASK		6
+#define EG_CB6_SIZE		7
+#define EG_CB6_PM4 128		
+
+/* EG_CB7 */
+#define EG_CB7__CB_COLOR7_BASE		0
+#define EG_CB7__CB_COLOR7_INFO		1
+#define EG_CB7__CB_COLOR7_SIZE		2
+#define EG_CB7__CB_COLOR7_VIEW		3
+#define EG_CB7__CB_COLOR7_FRAG		4
+#define EG_CB7__CB_COLOR7_TILE		5
+#define EG_CB7__CB_COLOR7_MASK		6
+#define EG_CB7_SIZE		7
+#define EG_CB7_PM4 128		
+
+/* EG_DB */
+#define EG_DB__DB_HTILE_DATA_BASE		0
+#define EG_DB__DB_Z_INFO		1
+#define EG_DB__DB_STENCIL_INFO		2
+#define EG_DB__DB_DEPTH_SIZE		3
+#define EG_DB__DB_DEPTH_SLICE		4
+#define EG_DB__DB_DEPTH_VIEW		5
+#define EG_DB__DB_HTILE_SURFACE		6
+#define EG_DB__DB_Z_READ_BASE		7
+#define EG_DB__DB_STENCIL_READ_BASE		8
+#define EG_DB__DB_Z_WRITE_BASE		9
+#define EG_DB__DB_STENCIL_WRITE_BASE		10
+#define EG_DB_SIZE		11
+#define EG_DB_PM4 128		
+
+/* EG_VGT */
+#define EG_VGT__VGT_PRIMITIVE_TYPE		0
+#define EG_VGT__VGT_MAX_VTX_INDX		1
+#define EG_VGT__VGT_MIN_VTX_INDX		2
+#define EG_VGT__VGT_INDX_OFFSET		3
+#define EG_VGT__VGT_DMA_INDEX_TYPE		4
+#define EG_VGT__VGT_PRIMITIVEID_EN		5
+#define EG_VGT__VGT_DMA_NUM_INSTANCES		6
+#define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN		7
+#define EG_VGT__VGT_INSTANCE_STEP_RATE_0		8
+#define EG_VGT__VGT_INSTANCE_STEP_RATE_1		9
+#define EG_VGT_SIZE		10
+#define EG_VGT_PM4 128		
+
+/* EG_DRAW */
+#define EG_DRAW__VGT_NUM_INDICES		0
+#define EG_DRAW__VGT_DMA_BASE_HI		1
+#define EG_DRAW__VGT_DMA_BASE		2
+#define EG_DRAW__VGT_DRAW_INITIATOR		3
+#define EG_DRAW_SIZE		4
+#define EG_DRAW_PM4 128		
+
+/* EG_VGT_EVENT */
+#define EG_VGT_EVENT__VGT_EVENT_INITIATOR		0
+#define EG_VGT_EVENT_SIZE		1
+#define EG_VGT_EVENT_PM4 128		
+
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
new file mode 100644
index 00000000000..6fab22107bd
--- /dev/null
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -0,0 +1,1442 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef EVERGREEND_H
+#define EVERGREEND_H
+
+#define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
+
+#define PKT3_NOP                               0x10
+#define PKT3_INDIRECT_BUFFER_END               0x17
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_REG_RMW                           0x21
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_START_3D_CMDBUF                   0x24
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_DRAW_INDEX_IMMD_BE                0x29
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX                        0x2B
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_INDIRECT_BUFFER_MP                0x38
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define PKT3_MEM_WRITE                         0x3D
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_CP_INTERRUPT                      0x40
+#define PKT3_SURFACE_SYNC                      0x43
+#define PKT3_ME_INITIALIZE                     0x44
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_ONE_REG_WRITE                     0x57
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_ALU_CONST                     0x6A
+#define PKT3_SET_BOOL_CONST                    0x6B
+#define PKT3_SET_LOOP_CONST                    0x6C
+#define PKT3_SET_RESOURCE                      0x6D
+#define PKT3_SET_SAMPLER                       0x6E
+#define PKT3_SET_CTL_CONST                     0x6F
+#define PKT3_SURFACE_BASE_UPDATE               0x73
+
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
+
+/* Registers */
+#define R_008C00_SQ_CONFIG                           0x00008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE(x)                        0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C(x)                     0xFFFFFFFD
+/* different */
+#define   S_008C00_CS_PRIO(x)                          (((x) & 0x3) << 18)
+#define   G_008C00_CS_PRIO(x)                          (((x) >> 18) & 0x3)
+#define   C_008C00_CS_PRIO(x)                          0xFFF3FFFF
+#define   S_008C00_LS_PRIO(x)                          (((x) & 0x3) << 20)
+#define   G_008C00_LS_PRIO(x)                          (((x) >> 20) & 0x3)
+#define   C_008C00_LS_PRIO(x)                          0xFFCFFFFF
+#define   S_008C00_HS_PRIO(x)                          (((x) & 0x3) << 22)
+#define   G_008C00_HS_PRIO(x)                          (((x) >> 22) & 0x3)
+#define   C_008C00_HS_PRIO(x)                          0xFF3FFFFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO(x)                          0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO(x)                          0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO(x)                          0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO(x)                          0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x00008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS(x)                      0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS(x)                      0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS(x)             0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x00008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS(x)                      0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS(x)                      0xFF00FFFF
+#define R_008C0C_SQ_GPR_RESOURCE_MGMT_3              0x00008C0C
+#define   S_008C0C_NUM_HS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_HS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_HS_GPRS(x)                      0xFFFFFF00
+#define   S_008C0C_NUM_LS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_LS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_LS_GPRS(x)                      0xFF00FFFF
+#define R_008C18_SQ_THREAD_RESOURCE_MGMT_1           0x00008C18
+#define   S_008C18_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C18_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C18_NUM_PS_THREADS(x)                   0xFFFFFF00
+#define   S_008C18_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C18_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C18_NUM_VS_THREADS(x)                   0xFFFF00FF
+#define   S_008C18_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C18_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C18_NUM_GS_THREADS(x)                   0xFF00FFFF
+#define   S_008C18_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C18_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C18_NUM_ES_THREADS(x)                   0x00FFFFFF
+#define R_008C1C_SQ_THREAD_RESOURCE_MGMT_2             0x00008C1C
+#define   S_008C1C_NUM_HS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C1C_NUM_HS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C1C_NUM_HS_THREADS(x)                   0xFFFFFF00
+#define   S_008C1C_NUM_LS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C1C_NUM_LS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C1C_NUM_LS_THREADS(x)                   0xFFFF00FF
+#define R_008C20_SQ_STACK_RESOURCE_MGMT_1            0x00008C20
+#define   S_008C20_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C20_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C20_NUM_PS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C20_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C20_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C20_NUM_VS_STACK_ENTRIES(x)             0xF000FFFF
+#define R_008C24_SQ_STACK_RESOURCE_MGMT_2            0x00008C24
+#define   S_008C24_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C24_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C24_NUM_GS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C24_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C24_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C24_NUM_ES_STACK_ENTRIES(x)             0xF000FFFF
+#define R_008C28_SQ_STACK_RESOURCE_MGMT_3            0x00008C28
+#define   S_008C28_NUM_HS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C28_NUM_HS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C28_NUM_HS_STACK_ENTRIES(x)             0xFFFFF000
+#define   S_008C28_NUM_LS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C28_NUM_LS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C28_NUM_LS_STACK_ENTRIES(x)             0xF000FFFF
+
+#define R_008CF0_SQ_MS_FIFO_SIZES                     0x00008CF0
+#define   S_008CF0_CACHE_FIFO_SIZE(x)                  (((x) & 0xFF) << 0)
+#define   G_008CF0_CACHE_FIFO_SIZE(x)                  (((x) >> 0) & 0xFF)
+#define   C_008CF0_CACHE_FIFO_SIZE(x)                  0xFFFFFF00
+#define   S_008CF0_FETCH_FIFO_HIWATER(x)               (((x) & 0x1F) << 8)
+#define   G_008CF0_FETCH_FIFO_HIWATER(x)               (((x) >> 8) & 0x1F)
+#define   C_008CF0_FETCH_FIFO_HIWATER(x)               0xFFFFE0FF
+#define   S_008CF0_DONE_FIFO_HIWATER(x)                (((x) & 0xFF) << 16)
+#define   G_008CF0_DONE_FIFO_HIWATER(x)                (((x) >> 16) & 0xFF)
+#define   C_008CF0_DONE_FIFO_HIWATER(x)                0xFF00FFFF
+#define   S_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          (((x) & 0x1F) << 24)
+#define   G_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          (((x) >> 24) & 0x1F)
+#define   C_008CF0_ALU_UPDATE_FIFO_HIWATER(x)          0xE0FFFFFF
+
+#define R_009100_SPI_CONFIG_CNTL                      0x00009100
+#define R_00913C_SPI_CONFIG_CNTL_1                    0x0000913C
+#define   S_00913C_VTX_DONE_DELAY(x)                (((x) & 0xF) << 0)
+#define   G_00913C_VTX_DONE_DELAY(x)                (((x) >> 0) & 0xF )
+#define   C_00913C_VTX_DONE_DELAY(x)                0xFFFFFFF0
+
+
+#define R_028C64_CB_COLOR0_PITCH                      0x028C64
+#define   S_028C64_PITCH_TILE_MAX(x)                   (((x) & 0x7FF) << 0)
+#define   G_028C64_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x7FF)
+#define   C_028C64_PITCH_TILE_MAX                      0xFFFFF800
+#define R_028C68_CB_COLOR0_SLICE                      0x028C68
+#define   S_028C68_SLICE_TILE_MAX(x)                   (((x) & 0x3FFFFF) << 0)
+#define   G_028C68_SLICE_TILE_MAX(x)                   (((x) >> 0) & 0x3FFFFF)
+#define   C_028C68_SLICE_TILE_MAX                      0xFFC00000
+#define R_028C70_CB_COLOR0_INFO                      0x028C70
+#define   S_028C70_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_028C70_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_028C70_ENDIAN                              0xFFFFFFFC
+#define   S_028C70_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_028C70_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_028C70_FORMAT                              0xFFFFFF03
+#define     V_028C70_COLOR_INVALID                     0x00000000
+#define     V_028C70_COLOR_8                           0x00000001
+#define     V_028C70_COLOR_4_4                         0x00000002
+#define     V_028C70_COLOR_3_3_2                       0x00000003
+#define     V_028C70_COLOR_16                          0x00000005
+#define     V_028C70_COLOR_16_FLOAT                    0x00000006
+#define     V_028C70_COLOR_8_8                         0x00000007
+#define     V_028C70_COLOR_5_6_5                       0x00000008
+#define     V_028C70_COLOR_6_5_5                       0x00000009
+#define     V_028C70_COLOR_1_5_5_5                     0x0000000A
+#define     V_028C70_COLOR_4_4_4_4                     0x0000000B
+#define     V_028C70_COLOR_5_5_5_1                     0x0000000C
+#define     V_028C70_COLOR_32                          0x0000000D
+#define     V_028C70_COLOR_32_FLOAT                    0x0000000E
+#define     V_028C70_COLOR_16_16                       0x0000000F
+#define     V_028C70_COLOR_16_16_FLOAT                 0x00000010
+#define     V_028C70_COLOR_8_24                        0x00000011
+#define     V_028C70_COLOR_8_24_FLOAT                  0x00000012
+#define     V_028C70_COLOR_24_8                        0x00000013
+#define     V_028C70_COLOR_24_8_FLOAT                  0x00000014
+#define     V_028C70_COLOR_10_11_11                    0x00000015
+#define     V_028C70_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_028C70_COLOR_11_11_10                    0x00000017
+#define     V_028C70_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_028C70_COLOR_2_10_10_10                  0x00000019
+#define     V_028C70_COLOR_8_8_8_8                     0x0000001A
+#define     V_028C70_COLOR_10_10_10_2                  0x0000001B
+#define     V_028C70_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_028C70_COLOR_32_32                       0x0000001D
+#define     V_028C70_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_028C70_COLOR_16_16_16_16                 0x0000001F
+#define     V_028C70_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_028C70_COLOR_32_32_32_32                 0x00000022
+#define     V_028C70_COLOR_32_32_32_32_FLOAT           0x00000023
+#define     V_028C70_COLOR_32_32_32_FLOAT              0x00000030
+#define   S_028C70_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_028C70_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_028C70_ARRAY_MODE                          0xFFFFF0FF
+#define     V_028C70_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_028C70_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_028C70_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_028C70_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_028C70_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_028C70_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_028C70_NUMBER_TYPE                         0xFFFF8FFF
+#define     V_028C70_NUMBER_UNORM                      0x00000000
+#define     V_028C70_NUMBER_SNORM                      0x00000001
+#define     V_028C70_NUMBER_USCALED                    0x00000002
+#define     V_028C70_NUMBER_SSCALED                    0x00000003
+#define     V_028C70_NUMBER_UINT                       0x00000004
+#define     V_028C70_NUMBER_SINT                       0x00000005
+#define     V_028C70_NUMBER_SRGB                       0x00000006
+#define     V_028C70_NUMBER_FLOAT                      0x00000007
+#define   S_028C70_COMP_SWAP(x)                        (((x) & 0x3) << 15)
+#define   G_028C70_COMP_SWAP(x)                        (((x) >> 15) & 0x3)
+#define   C_028C70_COMP_SWAP                           0xFFFE7FFF
+#define     V_028C70_SWAP_STD                          0x00000000
+#define     V_028C70_SWAP_ALT                          0x00000001
+#define     V_028C70_SWAP_STD_REV                      0x00000002
+#define     V_028C70_SWAP_ALT_REV                      0x00000003
+#define   S_028C70_FAST_CLEAR(x)                       (((x) & 0x1) << 17)
+#define   G_028C70_FAST_CLEAR(x)                       (((x) >> 17) & 0x1)
+#define   C_028C70_FAST_CLEAR                          0xFFFDFFFF
+#define   S_028C70_COMPRESSION(x)                      (((x) & 0x3) << 18)
+#define   G_028C70_COMPRESSION(x)                      (((x) >> 18) & 0x3)
+#define   C_028C70_COMPRESSION                         0xFFF3FFFF
+#define   S_028C70_BLEND_CLAMP(x)                      (((x) & 0x1) << 19)
+#define   G_028C70_BLEND_CLAMP(x)                      (((x) >> 19) & 0x1)
+#define   C_028C70_BLEND_CLAMP                         0xFFF7FFFF
+#define   S_028C70_BLEND_BYPASS(x)                     (((x) & 0x1) << 20)
+#define   G_028C70_BLEND_BYPASS(x)                     (((x) >> 20) & 0x1)
+#define   C_028C70_BLEND_BYPASS                        0xFFEFFFFF
+#define   S_028C70_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 21)
+#define   G_028C70_SIMPLE_FLOAT(x)                     (((x) >> 21) & 0x1)
+#define   C_028C70_SIMPLE_FLOAT                        0xFFDFFFFF
+#define   S_028C70_ROUND_MODE(x)                       (((x) & 0x1) << 22)
+#define   G_028C70_ROUND_MODE(x)                       (((x) >> 22) & 0x1)
+#define   C_028C70_ROUND_MODE                          0xFFBFFFFF
+#define   S_028C70_TILE_COMPACT(x)                     (((x) & 0x1) << 23)
+#define   G_028C70_TILE_COMPACT(x)                     (((x) >> 23) & 0x1)
+#define   C_028C70_TILE_COMPACT                        0xFF7FFFFF
+#define   S_028C70_SOURCE_FORMAT(x)                    (((x) & 0x3) << 24)
+#define   G_028C70_SOURCE_FORMAT(x)                    (((x) >> 24) & 0x3)
+#define   C_028C70_SOURCE_FORMAT                       0xFCFFFFFF
+#define   S_028C70_RAT(x)                              (((x) & 0x1) << 26)
+#define   G_028C70_RAT(x)                              (((x) >> 26) & 0x1)
+#define   C_028C70_RAT                                 0xFBFFFFFF
+#define   S_028C70_RESOURCE_TYPE(x)                    (((x) & 0x7) << 27)
+#define   G_028C70_RESOURCE_TYPE(x)                    (((x) >> 27) & 0x7)
+#define   C_028C70_RESOURCE_TYPE                       0xC7FFFFFF
+
+#define R_028C74_CB_COLOR0_ATTRIB                      0x028C74
+#define   S_028C74_NON_DISP_TILING_ORDER(x)            (((x) & 0x1) << 4)
+#define   G_028C74_NON_DISP_TILING_ORDER(x)            (((x) >> 4) & 0x1)
+#define   C_028C74_NON_DISP_TILING_ORDER               0xFFFFFFEF
+ 
+#define R_028C78_CB_COLOR0_DIM                         0x028C78
+#define   S_028C78_WIDTH_MAX(x)                        (((x) & 0xFFFF) << 0)
+#define   G_028C78_WIDTH_MAX(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_028C78_WIDTH_MAX                           0xFFFF0000
+#define   S_028C78_HEIGHT_MAX(x)                       (((x) & 0xFFFF) << 16)
+#define   G_028C78_HEIGHT_MAX(x)                       (((x) >> 16) & 0xFFFF)
+#define   C_028C78_HEIGHT_MAX                          0x0000FFFF
+
+#define R_028C7C_CB_COLOR0_CMASK                         0x028C7C
+#define R_028C80_CB_COLOR0_CMASK_SLICE                   0x028C80
+#define R_028C84_CB_COLOR0_FMASK                         0x028C84
+#define R_028C88_CB_COLOR0_FMASK_SLICE                   0x028C88
+
+#define R_028C8C_CB_COLOR0_CLEAR_WORD0                   0x028C8C
+#define R_028C90_CB_COLOR0_CLEAR_WORD1                   0x028C90
+#define R_028C94_CB_COLOR0_CLEAR_WORD2                   0x028C94
+#define R_028C98_CB_COLOR0_CLEAR_WORD3                   0x028C98
+
+/* alpha same */
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define     V_028800_STENCILFUNC_NEVER                 0x00000000
+#define     V_028800_STENCILFUNC_LESS                  0x00000001
+#define     V_028800_STENCILFUNC_EQUAL                 0x00000002
+#define     V_028800_STENCILFUNC_LEQUAL                0x00000003
+#define     V_028800_STENCILFUNC_GREATER               0x00000004
+#define     V_028800_STENCILFUNC_NOTEQUAL              0x00000005
+#define     V_028800_STENCILFUNC_GEQUAL                0x00000006
+#define     V_028800_STENCILFUNC_ALWAYS                0x00000007
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define     V_028800_STENCIL_KEEP                      0x00000000
+#define     V_028800_STENCIL_ZERO                      0x00000001
+#define     V_028800_STENCIL_REPLACE                   0x00000002
+#define     V_028800_STENCIL_INCR                      0x00000003
+#define     V_028800_STENCIL_DECR                      0x00000004
+#define     V_028800_STENCIL_INVERT                    0x00000005
+#define     V_028800_STENCIL_INCR_WRAP                 0x00000006
+#define     V_028800_STENCIL_DECR_WRAP                 0x00000007
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_MODE(x)                             (((x) & 0x7) << 4)
+#define   G_028808_MODE(x)                             (((x) >> 4) & 0x7)
+#define   C_028808_MODE                                0xFFFFFF8F
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define   S_028810_UCP_ENA_0(x)                        (((x) & 0x1) << 0)
+#define   G_028810_UCP_ENA_0(x)                        (((x) >> 0) & 0x1)
+#define   C_028810_UCP_ENA_0                           0xFFFFFFFE
+#define   S_028810_UCP_ENA_1(x)                        (((x) & 0x1) << 1)
+#define   G_028810_UCP_ENA_1(x)                        (((x) >> 1) & 0x1)
+#define   C_028810_UCP_ENA_1                           0xFFFFFFFD
+#define   S_028810_UCP_ENA_2(x)                        (((x) & 0x1) << 2)
+#define   G_028810_UCP_ENA_2(x)                        (((x) >> 2) & 0x1)
+#define   C_028810_UCP_ENA_2                           0xFFFFFFFB
+#define   S_028810_UCP_ENA_3(x)                        (((x) & 0x1) << 3)
+#define   G_028810_UCP_ENA_3(x)                        (((x) >> 3) & 0x1)
+#define   C_028810_UCP_ENA_3                           0xFFFFFFF7
+#define   S_028810_UCP_ENA_4(x)                        (((x) & 0x1) << 4)
+#define   G_028810_UCP_ENA_4(x)                        (((x) >> 4) & 0x1)
+#define   C_028810_UCP_ENA_4                           0xFFFFFFEF
+#define   S_028810_UCP_ENA_5(x)                        (((x) & 0x1) << 5)
+#define   G_028810_UCP_ENA_5(x)                        (((x) >> 5) & 0x1)
+#define   C_028810_UCP_ENA_5                           0xFFFFFFDF
+#define   S_028810_PS_UCP_Y_SCALE_NEG(x)               (((x) & 0x1) << 13)
+#define   G_028810_PS_UCP_Y_SCALE_NEG(x)               (((x) >> 13) & 0x1)
+#define   C_028810_PS_UCP_Y_SCALE_NEG                  0xFFFFDFFF
+#define   S_028810_PS_UCP_MODE(x)                      (((x) & 0x3) << 14)
+#define   G_028810_PS_UCP_MODE(x)                      (((x) >> 14) & 0x3)
+#define   C_028810_PS_UCP_MODE                         0xFFFF3FFF
+#define   S_028810_CLIP_DISABLE(x)                     (((x) & 0x1) << 16)
+#define   G_028810_CLIP_DISABLE(x)                     (((x) >> 16) & 0x1)
+#define   C_028810_CLIP_DISABLE                        0xFFFEFFFF
+#define   S_028810_UCP_CULL_ONLY_ENA(x)                (((x) & 0x1) << 17)
+#define   G_028810_UCP_CULL_ONLY_ENA(x)                (((x) >> 17) & 0x1)
+#define   C_028810_UCP_CULL_ONLY_ENA                   0xFFFDFFFF
+#define   S_028810_BOUNDARY_EDGE_FLAG_ENA(x)           (((x) & 0x1) << 18)
+#define   G_028810_BOUNDARY_EDGE_FLAG_ENA(x)           (((x) >> 18) & 0x1)
+#define   C_028810_BOUNDARY_EDGE_FLAG_ENA              0xFFFBFFFF
+#define   S_028810_DX_CLIP_SPACE_DEF(x)                (((x) & 0x1) << 19)
+#define   G_028810_DX_CLIP_SPACE_DEF(x)                (((x) >> 19) & 0x1)
+#define   C_028810_DX_CLIP_SPACE_DEF                   0xFFF7FFFF
+#define   S_028810_DIS_CLIP_ERR_DETECT(x)              (((x) & 0x1) << 20)
+#define   G_028810_DIS_CLIP_ERR_DETECT(x)              (((x) >> 20) & 0x1)
+#define   C_028810_DIS_CLIP_ERR_DETECT                 0xFFEFFFFF
+#define   S_028810_VTX_KILL_OR(x)                      (((x) & 0x1) << 21)
+#define   G_028810_VTX_KILL_OR(x)                      (((x) >> 21) & 0x1)
+#define   C_028810_VTX_KILL_OR                         0xFFDFFFFF
+#define   S_028810_DX_LINEAR_ATTR_CLIP_ENA(x)          (((x) & 0x1) << 24)
+#define   G_028810_DX_LINEAR_ATTR_CLIP_ENA(x)          (((x) >> 24) & 0x1)
+#define   C_028810_DX_LINEAR_ATTR_CLIP_ENA             0xFEFFFFFF
+#define   S_028810_VTE_VPORT_PROVOKE_DISABLE(x)        (((x) & 0x1) << 25)
+#define   G_028810_VTE_VPORT_PROVOKE_DISABLE(x)        (((x) >> 25) & 0x1)
+#define   C_028810_VTE_VPORT_PROVOKE_DISABLE           0xFDFFFFFF
+#define   S_028810_ZCLIP_NEAR_DISABLE(x)               (((x) & 0x1) << 26)
+#define   G_028810_ZCLIP_NEAR_DISABLE(x)               (((x) >> 26) & 0x1)
+#define   C_028810_ZCLIP_NEAR_DISABLE                  0xFBFFFFFF
+#define   S_028810_ZCLIP_FAR_DISABLE(x)                (((x) & 0x1) << 27)
+#define   G_028810_ZCLIP_FAR_DISABLE(x)                (((x) >> 27) & 0x1)
+#define   C_028810_ZCLIP_FAR_DISABLE                   0xF7FFFFFF
+
+#define R_028040_DB_Z_INFO                       0x028040
+#define   S_028040_FORMAT(x)                           (((x) & 0x3) << 0)
+#define   G_028040_FORMAT(x)                           (((x) >> 0) & 0x3)
+#define   C_028040_FORMAT                              0xFFFFFFFC
+#define     V_028040_Z_INVALID                     0x00000000
+#define     V_028040_Z_16                          0x00000001
+#define     V_028040_Z_24                          0x00000002
+#define     V_028040_Z_32_FLOAT                    0x00000003
+#define   S_028040_ARRAY_MODE(x)                       (((x) & 0xF) << 4)
+#define   G_028040_ARRAY_MODE(x)                       (((x) >> 4) & 0xF)
+#define   C_028040_ARRAY_MODE                          0xFFFFFF0F
+#define   S_028040_READ_SIZE(x)                        (((x) & 0x1) << 28)
+#define   G_028040_READ_SIZE(x)                        (((x) >> 28) & 0x1)
+#define   C_028040_READ_SIZE                           0xEFFFFFFF
+#define   S_028040_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 29)
+#define   G_028040_TILE_SURFACE_ENABLE(x)              (((x) >> 29) & 0x1)
+#define   C_028040_TILE_SURFACE_ENABLE                 0xDFFFFFFF
+#define   S_028040_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028040_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028040_ZRANGE_PRECISION                    0x7FFFFFFF
+
+#define R_028044_DB_STENCIL_INFO                     0x028044
+#define   S_028044_FORMAT(x)                           (((x) & 0x1) << 0)
+#define   G_028044_FORMAT(x)                           (((x) >> 0) & 0x1)
+#define   C_028044_FORMAT                              0xFFFFFFFE
+
+#define R_028058_DB_DEPTH_SIZE                       0x028058
+#define   S_028058_PITCH_TILE_MAX(x)                   (((x) & 0x7FF) << 0)
+#define   G_028058_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x7FF)
+#define   C_028058_PITCH_TILE_MAX                      0xFFFFF800
+#define   S_028058_HEIGHT_TILE_MAX(x)                   (((x) & 0x7FF) << 11)
+#define   G_028058_HEIGHT_TILE_MAX(x)                   (((x) >> 11) & 0x7FF)
+#define   C_028058_HEIGHT_TILE_MAX                      0xFFC007FF
+
+#define R_02805C_DB_DEPTH_SLICE                      0x02805C
+#define   S_02805C_SLICE_TILE_MAX(x)                   (((x) & 0x3FFFFF) << 0)
+#define   G_02805C_SLICE_TILE_MAX(x)                   (((x) >> 0) & 0x3FFFFF)
+#define   C_02805C_SLICE_TILE_MAX                      0xFFC00000
+
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define   S_028430_STENCILREF(x)                       (((x) & 0xFF) << 0)
+#define   G_028430_STENCILREF(x)                       (((x) >> 0) & 0xFF)
+#define   C_028430_STENCILREF                          0xFFFFFF00
+#define   S_028430_STENCILMASK(x)                      (((x) & 0xFF) << 8)
+#define   G_028430_STENCILMASK(x)                      (((x) >> 8) & 0xFF)
+#define   C_028430_STENCILMASK                         0xFFFF00FF
+#define   S_028430_STENCILWRITEMASK(x)                 (((x) & 0xFF) << 16)
+#define   G_028430_STENCILWRITEMASK(x)                 (((x) >> 16) & 0xFF)
+#define   C_028430_STENCILWRITEMASK                    0xFF00FFFF
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define   S_028434_STENCILREF_BF(x)                    (((x) & 0xFF) << 0)
+#define   G_028434_STENCILREF_BF(x)                    (((x) >> 0) & 0xFF)
+#define   C_028434_STENCILREF_BF                       0xFFFFFF00
+#define   S_028434_STENCILMASK_BF(x)                   (((x) & 0xFF) << 8)
+#define   G_028434_STENCILMASK_BF(x)                   (((x) >> 8) & 0xFF)
+#define   C_028434_STENCILMASK_BF                      0xFFFF00FF
+#define   S_028434_STENCILWRITEMASK_BF(x)              (((x) & 0xFF) << 16)
+#define   G_028434_STENCILWRITEMASK_BF(x)              (((x) >> 16) & 0xFF)
+#define   C_028434_STENCILWRITEMASK_BF                 0xFF00FFFF
+#define R_028780_CB_BLEND_CONTROL                    0x028780
+#define   S_028780_COLOR_SRCBLEND(x)                   (((x) & 0x1F) << 0)
+#define   G_028780_COLOR_SRCBLEND(x)                   (((x) >> 0) & 0x1F)
+#define   C_028780_COLOR_SRCBLEND                      0xFFFFFFE0
+#define     V_028780_BLEND_ZERO                        0x00000000
+#define     V_028780_BLEND_ONE                         0x00000001
+#define     V_028780_BLEND_SRC_COLOR                   0x00000002
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR         0x00000003
+#define     V_028780_BLEND_SRC_ALPHA                   0x00000004
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA         0x00000005
+#define     V_028780_BLEND_DST_ALPHA                   0x00000006
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA         0x00000007
+#define     V_028780_BLEND_DST_COLOR                   0x00000008
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR         0x00000009
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE          0x0000000A
+#define     V_028780_BLEND_BOTH_SRC_ALPHA              0x0000000B
+#define     V_028780_BLEND_BOTH_INV_SRC_ALPHA          0x0000000C
+#define     V_028780_BLEND_CONST_COLOR                 0x0000000D
+#define     V_028780_BLEND_ONE_MINUS_CONST_COLOR       0x0000000E
+#define     V_028780_BLEND_SRC1_COLOR                  0x0000000F
+#define     V_028780_BLEND_INV_SRC1_COLOR              0x00000010
+#define     V_028780_BLEND_SRC1_ALPHA                  0x00000011
+#define     V_028780_BLEND_INV_SRC1_ALPHA              0x00000012
+#define     V_028780_BLEND_CONST_ALPHA                 0x00000013
+#define     V_028780_BLEND_ONE_MINUS_CONST_ALPHA       0x00000014
+#define   S_028780_COLOR_COMB_FCN(x)                   (((x) & 0x7) << 5)
+#define   G_028780_COLOR_COMB_FCN(x)                   (((x) >> 5) & 0x7)
+#define   C_028780_COLOR_COMB_FCN                      0xFFFFFF1F
+#define     V_028780_COMB_DST_PLUS_SRC                 0x00000000
+#define     V_028780_COMB_SRC_MINUS_DST                0x00000001
+#define     V_028780_COMB_MIN_DST_SRC                  0x00000002
+#define     V_028780_COMB_MAX_DST_SRC                  0x00000003
+#define     V_028780_COMB_DST_MINUS_SRC                0x00000004
+#define   S_028780_COLOR_DESTBLEND(x)                  (((x) & 0x1F) << 8)
+#define   G_028780_COLOR_DESTBLEND(x)                  (((x) >> 8) & 0x1F)
+#define   C_028780_COLOR_DESTBLEND                     0xFFFFE0FF
+#define   S_028780_OPACITY_WEIGHT(x)                   (((x) & 0x1) << 13)
+#define   G_028780_OPACITY_WEIGHT(x)                   (((x) >> 13) & 0x1)
+#define   C_028780_OPACITY_WEIGHT                      0xFFFFDFFF
+#define   S_028780_ALPHA_SRCBLEND(x)                   (((x) & 0x1F) << 16)
+#define   G_028780_ALPHA_SRCBLEND(x)                   (((x) >> 16) & 0x1F)
+#define   C_028780_ALPHA_SRCBLEND                      0xFFE0FFFF
+#define   S_028780_ALPHA_COMB_FCN(x)                   (((x) & 0x7) << 21)
+#define   G_028780_ALPHA_COMB_FCN(x)                   (((x) >> 21) & 0x7)
+#define   C_028780_ALPHA_COMB_FCN                      0xFF1FFFFF
+#define   S_028780_ALPHA_DESTBLEND(x)                  (((x) & 0x1F) << 24)
+#define   G_028780_ALPHA_DESTBLEND(x)                  (((x) >> 24) & 0x1F)
+#define   C_028780_ALPHA_DESTBLEND                     0xE0FFFFFF
+#define   S_028780_SEPARATE_ALPHA_BLEND(x)             (((x) & 0x1) << 29)
+#define   G_028780_SEPARATE_ALPHA_BLEND(x)             (((x) >> 29) & 0x1)
+#define   C_028780_SEPARATE_ALPHA_BLEND                0xDFFFFFFF
+#define   S_028780_BLEND_CONTROL_ENABLE(x)             (((x) & 0x1) << 30)
+#define   G_028780_BLEND_CONTROL_ENABLE(x)             (((x) >> 30) & 0x1)
+#define   C_028780_BLEND_CONTROL_ENABLE                0xEFFFFFFF
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define   S_028814_CULL_FRONT(x)                       (((x) & 0x1) << 0)
+#define   G_028814_CULL_FRONT(x)                       (((x) >> 0) & 0x1)
+#define   C_028814_CULL_FRONT                          0xFFFFFFFE
+#define   S_028814_CULL_BACK(x)                        (((x) & 0x1) << 1)
+#define   G_028814_CULL_BACK(x)                        (((x) >> 1) & 0x1)
+#define   C_028814_CULL_BACK                           0xFFFFFFFD
+#define   S_028814_FACE(x)                             (((x) & 0x1) << 2)
+#define   G_028814_FACE(x)                             (((x) >> 2) & 0x1)
+#define   C_028814_FACE                                0xFFFFFFFB
+#define   S_028814_POLY_MODE(x)                        (((x) & 0x3) << 3)
+#define   G_028814_POLY_MODE(x)                        (((x) >> 3) & 0x3)
+#define   C_028814_POLY_MODE                           0xFFFFFFE7
+#define   S_028814_POLYMODE_FRONT_PTYPE(x)             (((x) & 0x7) << 5)
+#define   G_028814_POLYMODE_FRONT_PTYPE(x)             (((x) >> 5) & 0x7)
+#define   C_028814_POLYMODE_FRONT_PTYPE                0xFFFFFF1F
+#define   S_028814_POLYMODE_BACK_PTYPE(x)              (((x) & 0x7) << 8)
+#define   G_028814_POLYMODE_BACK_PTYPE(x)              (((x) >> 8) & 0x7)
+#define   C_028814_POLYMODE_BACK_PTYPE                 0xFFFFF8FF
+#define   S_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) & 0x1) << 11)
+#define   G_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) >> 11) & 0x1)
+#define   C_028814_POLY_OFFSET_FRONT_ENABLE            0xFFFFF7FF
+#define   S_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) & 0x1) << 12)
+#define   G_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) >> 12) & 0x1)
+#define   C_028814_POLY_OFFSET_BACK_ENABLE             0xFFFFEFFF
+#define   S_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) & 0x1) << 13)
+#define   G_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) >> 13) & 0x1)
+#define   C_028814_POLY_OFFSET_PARA_ENABLE             0xFFFFDFFF
+#define   S_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) & 0x1) << 16)
+#define   G_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) >> 16) & 0x1)
+#define   C_028814_VTX_WINDOW_OFFSET_ENABLE            0xFFFEFFFF
+#define   S_028814_PROVOKING_VTX_LAST(x)               (((x) & 0x1) << 19)
+#define   G_028814_PROVOKING_VTX_LAST(x)               (((x) >> 19) & 0x1)
+#define   C_028814_PROVOKING_VTX_LAST                  0xFFF7FFFF
+#define   S_028814_PERSP_CORR_DIS(x)                   (((x) & 0x1) << 20)
+#define   G_028814_PERSP_CORR_DIS(x)                   (((x) >> 20) & 0x1)
+#define   C_028814_PERSP_CORR_DIS                      0xFFEFFFFF
+#define   S_028814_MULTI_PRIM_IB_ENA(x)                (((x) & 0x1) << 21)
+#define   G_028814_MULTI_PRIM_IB_ENA(x)                (((x) >> 21) & 0x1)
+#define   C_028814_MULTI_PRIM_IB_ENA                   0xFFDFFFFF
+
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
+#define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028D0C_R700_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   V_028D10_FORCE_OFF                         0
+#define   V_028D10_FORCE_ENABLE                      1
+#define   V_028D10_FORCE_DISABLE                     2
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E00_SCALE                               0x00000000
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E04_OFFSET                              0x00000000
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E08_SCALE                               0x00000000
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E0C_OFFSET                              0x00000000
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
+#define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_028A00_HEIGHT                              0xFFFF0000
+#define   S_028A00_WIDTH(x)                            (((x) & 0xFFFF) << 16)
+#define   G_028A00_WIDTH(x)                            (((x) >> 16) & 0xFFFF)
+#define   C_028A00_WIDTH                               0x0000FFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+
+/* diff */
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+
+#define R_0286E0_SPI_BARYC_CNTL                     0x0286E0
+#define   S_0286E0_PERSP_CENTER_ENA(x)                (((x) & 0x3) << 0)
+#define   G_0286E0_PERSP_CENTER_ENA(x)                (((x) >> 0) & 0x3)
+#define   C_0286E0_PERSP_CENTER_ENA                   0xFFFFFFFC
+#define   S_0286E0_PERSP_CENTROID_ENA(x)              (((x) & 0x3) << 4)
+#define   G_0286E0_PERSP_CENTROID_ENA(x)              (((x) >> 4) & 0x3)
+#define   C_0286E0_PERSP_CENTROID_ENA                 0xFFFFFFCF
+#define   S_0286E0_PERSP_SAMPLE_ENA(x)                (((x) & 0x3) << 8)
+#define   G_0286E0_PERSP_SAMPLE_ENA(x)                (((x) >> 8) & 0x3)
+#define   C_0286E0_PERSP_SAMPLE_ENA                   0xFFFFFCFF
+#define   S_0286E0_PERSP_PULL_MODEL_ENA(x)            (((x) & 0x3) << 12)
+#define   G_0286E0_PERSP_PULL_MODEL_ENA(x)            (((x) >> 12) & 0x3)
+#define   C_0286E0_PERSP_PULL_MODEL_ENA               0xFFFFCFFF
+#define   S_0286E0_LINEAR_CENTER_ENA(x)               (((x) & 0x3) << 16)
+#define   G_0286E0_LINEAR_CENTER_ENA(x)               (((x) >> 16) & 0x3)
+#define   C_0286E0_LINEAR_CENTER_ENA                  0xFFFCFFFF
+#define   S_0286E0_LINEAR_CENTROID_ENA(x)             (((x) & 0x3) << 20)
+#define   G_0286E0_LINEAR_CENTROID_ENA(x)             (((x) >> 20) & 0x3)
+#define   C_0286E0_LINEAR_CENTROID_ENA                0xFFCFFFFF
+#define   S_0286E0_LINEAR_SAMPLE_ENA(x)               (((x) & 0x3) << 24)
+#define   G_0286E0_LINEAR_SAMPLE_ENA(x)               (((x) >> 24) & 0x3)
+#define   C_0286E0_LINEAR_SAMPLE_ENA                  0xFCFFFFFF
+
+
+/* new - diff */
+#define R_028250_PA_SC_VPORT_SCISSOR_TL                0x028250
+#define   S_028250_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028250_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028250_TL_X                                0xFFFF8000
+#define   S_028250_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028250_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028250_TL_Y                                0x8000FFFF
+#define   S_028250_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028250_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028250_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028254_PA_SC_VPORT_SCISSOR_BR                0x028254
+#define   S_028254_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028254_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028254_BR_X                                0xFFFF8000
+#define   S_028254_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028254_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028254_BR_Y                                0x8000FFFF
+/* diff */
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028240_TL_X                                0xFFFF8000
+#define   S_028240_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028240_TL_Y                                0x8000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028244_BR_X                                0xFFFF8000
+#define   S_028244_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028244_BR_Y                                0x8000FFFF
+/* diff */
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0xFFFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0xFFFF)
+#define   C_028030_TL_X                                0xFFFF0000
+#define   S_028030_TL_Y(x)                             (((x) & 0xFFFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0xFFFF)
+#define   C_028030_TL_Y                                0x0000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0xFFFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0xFFFF)
+#define   C_028034_BR_X                                0xFFFF0000
+#define   S_028034_BR_Y(x)                             (((x) & 0xFFFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0xFFFF)
+#define   C_028034_BR_Y                                0x0000FFFF
+/* diff */
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028204_TL_X                                0xFFFF8000
+#define   S_028204_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028204_TL_Y                                0x8000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028208_BR_X                                0xFFFF8000
+#define   S_028208_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028208_BR_Y                                0x8000FFFF
+
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+
+#define R_030000_SQ_TEX_RESOURCE_WORD0_0             0x030000
+#define   S_030000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_030000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_030000_DIM                                 0xFFFFFFF8
+#define     V_030000_SQ_TEX_DIM_1D                     0x00000000
+#define     V_030000_SQ_TEX_DIM_2D                     0x00000001
+#define     V_030000_SQ_TEX_DIM_3D                     0x00000002
+#define     V_030000_SQ_TEX_DIM_CUBEMAP                0x00000003
+#define     V_030000_SQ_TEX_DIM_1D_ARRAY               0x00000004
+#define     V_030000_SQ_TEX_DIM_2D_ARRAY               0x00000005
+#define     V_030000_SQ_TEX_DIM_2D_MSAA                0x00000006
+#define     V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
+#define   S_030000_PITCH(x)                            (((x) & 0xFFF) << 6)
+#define   G_030000_PITCH(x)                            (((x) >> 6) & 0xFFF)
+#define   C_030000_PITCH                               0xFFFC003F
+#define   S_030000_TEX_WIDTH(x)                        (((x) & 0x3FFF) << 18)
+#define   G_030000_TEX_WIDTH(x)                        (((x) >> 18) & 0x3FFF)
+#define   C_030000_TEX_WIDTH                           0x0003FFFF
+#define R_030004_SQ_TEX_RESOURCE_WORD1_0             0x030004
+#define   S_030004_TEX_HEIGHT(x)                       (((x) & 0x3FFF) << 0)
+#define   G_030004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x3FFF)
+#define   C_030004_TEX_HEIGHT                          0xFFFFC000
+#define   S_030004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 14)
+#define   G_030004_TEX_DEPTH(x)                        (((x) >> 14) & 0x1FFF)
+#define   C_030004_TEX_DEPTH                           0xF8003FFF
+#define   S_030004_ARRAY_MODE(x)                       (((x) & 0xF) << 28)
+#define   G_030004_ARRAY_MODE(x)                       (((x) >> 28) & 0xF)
+#define   C_030004_ARRAY_MODE                          0x0FFFFFFF
+#define R_030008_SQ_TEX_RESOURCE_WORD2_0             0x030008
+#define   S_030008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_BASE_ADDRESS                        0x00000000
+#define R_03000C_SQ_TEX_RESOURCE_WORD3_0             0x03000C
+#define   S_03000C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_MIP_ADDRESS                         0x00000000
+#define R_030010_SQ_TEX_RESOURCE_WORD4_0             0x030010
+#define   S_030010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_030010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_030010_FORMAT_COMP_X                       0xFFFFFFFC
+#define     V_030010_SQ_FORMAT_COMP_UNSIGNED           0x00000000
+#define     V_030010_SQ_FORMAT_COMP_SIGNED             0x00000001
+#define     V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED    0x00000002
+#define   S_030010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_030010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_030010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_030010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_030010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_030010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_030010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_030010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_030010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_030010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_030010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_030010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define     V_030010_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_030010_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_030010_SQ_NUM_FORMAT_SCALED              0x00000002
+#define   S_030010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_030010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_030010_SRF_MODE_ALL                        0xFFFFFBFF
+#define     V_030010_SFR_MODE_ZERO_CLAMP_MINUS_ONE     0x00000000
+#define     V_030010_SFR_MODE_NO_ZERO                  0x00000001
+#define   S_030010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_030010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_030010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_030010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_030010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_030010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_030010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_030010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_030010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_030010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_030010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_030010_DST_SEL_X                           0xFFF8FFFF
+#define     V_030010_SQ_SEL_X                          0x00000000
+#define     V_030010_SQ_SEL_Y                          0x00000001
+#define     V_030010_SQ_SEL_Z                          0x00000002
+#define     V_030010_SQ_SEL_W                          0x00000003
+#define     V_030010_SQ_SEL_0                          0x00000004
+#define     V_030010_SQ_SEL_1                          0x00000005
+#define   S_030010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_030010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_030010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_030010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_030010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_030010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_030010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_030010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_030010_DST_SEL_W                           0xF1FFFFFF
+#define   S_030010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_030010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_030010_BASE_LEVEL                          0x0FFFFFFF
+#define R_030014_SQ_TEX_RESOURCE_WORD5_0             0x030014
+#define   S_030014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_030014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_030014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_030014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_030014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_030014_BASE_ARRAY                          0xFFFE000F
+#define   S_030014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_030014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_030014_LAST_ARRAY                          0xC001FFFF
+#define R_030018_SQ_TEX_RESOURCE_WORD6_0             0x030018
+#define   S_030018_PERF_MODULATION(x)                  (((x) & 0x7) << 3)
+#define   G_030018_PERF_MODULATION(x)                  (((x) >> 3) & 0x7)
+#define   C_030018_PERF_MODULATION                     0xFFFFFFC7
+#define   S_030018_INTERLACED(x)                       (((x) & 0x1) << 6)
+#define   G_030018_INTERLACED(x)                       (((x) >> 6) & 0x1)
+#define   C_030018_INTERLACED                          0xFFFFFFBF
+#define R_03001C_SQ_TEX_RESOURCE_WORD7_0             0x03001C
+#define   S_03001C_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_03001C_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_03001C_TYPE                                0x3FFFFFFF
+#define     V_03001C_SQ_TEX_VTX_INVALID_TEXTURE        0x00000000
+#define     V_03001C_SQ_TEX_VTX_INVALID_BUFFER         0x00000001
+#define     V_03001C_SQ_TEX_VTX_VALID_TEXTURE          0x00000002
+#define     V_03001C_SQ_TEX_VTX_VALID_BUFFER           0x00000003
+#define   S_03001C_DATA_FORMAT(x)                      (((x) & 0x3F) << 0)
+#define   G_03001C_DATA_FORMAT(x)                      (((x) >> 0) & 0x3F)
+#define   C_03001C_DATA_FORMAT                         0xFFFFFFC0
+
+#define R_030008_SQ_VTX_CONSTANT_WORD2_0             0x030008
+#define   S_030008_BASE_ADDRESS_HI(x)                  (((x) & 0xFF) << 0)
+#define   G_030008_BASE_ADDRESS_HI(x)                  (((x) >> 0) & 0xFF)
+#define   C_030008_BASE_ADDRESS_HI                     0xFFFFFF00
+#define   S_030008_STRIDE(x)                           (((x) & 0x7FF) << 8)
+#define   G_030008_STRIDE(x)                           (((x) >> 8) & 0x7FF)
+#define   C_030008_STRIDE                              0xFFF800FF
+#define   S_030008_CLAMP_X(x)                          (((x) & 0x1) << 19)
+#define   G_030008_CLAMP_X(x)                          (((x) >> 19) & 0x1)
+#define   C_030008_CLAMP_X                             0xFFF7FFFF
+#define   S_030008_DATA_FORMAT(x)                      (((x) & 0x3F) << 20)
+#define   G_030008_DATA_FORMAT(x)                      (((x) >> 20) & 0x3F)
+#define   C_030008_DATA_FORMAT                         0xFC0FFFFF
+#define     V_030008_COLOR_INVALID                     0x00000000
+#define     V_030008_COLOR_8                           0x00000001
+#define     V_030008_COLOR_4_4                         0x00000002
+#define     V_030008_COLOR_3_3_2                       0x00000003
+#define     V_030008_COLOR_16                          0x00000005
+#define     V_030008_COLOR_16_FLOAT                    0x00000006
+#define     V_030008_COLOR_8_8                         0x00000007
+#define     V_030008_COLOR_5_6_5                       0x00000008
+#define     V_030008_COLOR_6_5_5                       0x00000009
+#define     V_030008_COLOR_1_5_5_5                     0x0000000A
+#define     V_030008_COLOR_4_4_4_4                     0x0000000B
+#define     V_030008_COLOR_5_5_5_1                     0x0000000C
+#define     V_030008_COLOR_32                          0x0000000D
+#define     V_030008_COLOR_32_FLOAT                    0x0000000E
+#define     V_030008_COLOR_16_16                       0x0000000F
+#define     V_030008_COLOR_16_16_FLOAT                 0x00000010
+#define     V_030008_COLOR_8_24                        0x00000011
+#define     V_030008_COLOR_8_24_FLOAT                  0x00000012
+#define     V_030008_COLOR_24_8                        0x00000013
+#define     V_030008_COLOR_24_8_FLOAT                  0x00000014
+#define     V_030008_COLOR_10_11_11                    0x00000015
+#define     V_030008_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_030008_COLOR_11_11_10                    0x00000017
+#define     V_030008_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_030008_COLOR_2_10_10_10                  0x00000019
+#define     V_030008_COLOR_8_8_8_8                     0x0000001A
+#define     V_030008_COLOR_10_10_10_2                  0x0000001B
+#define     V_030008_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_030008_COLOR_32_32                       0x0000001D
+#define     V_030008_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_030008_COLOR_16_16_16_16                 0x0000001F
+#define     V_030008_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_030008_COLOR_32_32_32_32                 0x00000022
+#define     V_030008_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_030008_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 26)
+#define   G_030008_NUM_FORMAT_ALL(x)                   (((x) >> 26) & 0x3)
+#define   C_030008_NUM_FORMAT_ALL                      0xF3FFFFFF
+#define   S_030008_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 28)
+#define   G_030008_FORMAT_COMP_ALL(x)                  (((x) >> 28) & 0x1)
+#define   C_030008_FORMAT_COMP_ALL                     0xEFFFFFFF
+#define   S_030008_SRF_MODE_ALL(x)                     (((x) & 0x1) << 29)
+#define   G_030008_SRF_MODE_ALL(x)                     (((x) >> 29) & 0x1)
+#define   C_030008_SRF_MODE_ALL                        0xDFFFFFFF
+#define   S_030008_ENDIAN_SWAP(x)                      (((x) & 0x3) << 30)
+#define   G_030008_ENDIAN_SWAP(x)                      (((x) >> 30) & 0x3)
+#define   C_030008_ENDIAN_SWAP                         0x3FFFFFFF
+
+#define R_03000C_SQ_VTX_CONSTANT_WORD3_0             0x03000C
+#define   S_03000C_DST_SEL_X(x)                        (((x) & 0x7) << 3)
+#define   G_03000C_DST_SEL_X(x)                        (((x) >> 3) & 0x7)
+#define     V_03000C_SQ_SEL_X                          0x00000000
+#define     V_03000C_SQ_SEL_Y                          0x00000001
+#define     V_03000C_SQ_SEL_Z                          0x00000002
+#define     V_03000C_SQ_SEL_W                          0x00000003
+#define     V_03000C_SQ_SEL_0                          0x00000004
+#define     V_03000C_SQ_SEL_1                          0x00000005
+#define   S_03000C_DST_SEL_Y(x)                        (((x) & 0x7) << 6)
+#define   G_03000C_DST_SEL_Y(x)                        (((x) >> 6) & 0x7)
+#define   S_03000C_DST_SEL_Z(x)                        (((x) & 0x7) << 9)
+#define   G_03000C_DST_SEL_Z(x)                        (((x) >> 9) & 0x7)
+#define   S_03000C_DST_SEL_W(x)                        (((x) & 0x7) << 12)
+#define   G_03000C_DST_SEL_W(x)                        (((x) >> 12) & 0x7)
+
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define     V_03C000_SQ_TEX_WRAP                       0x00000000
+#define     V_03C000_SQ_TEX_MIRROR                     0x00000001
+#define     V_03C000_SQ_TEX_CLAMP_LAST_TEXEL           0x00000002
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL     0x00000003
+#define     V_03C000_SQ_TEX_CLAMP_HALF_BORDER          0x00000004
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER    0x00000005
+#define     V_03C000_SQ_TEX_CLAMP_BORDER               0x00000006
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_BORDER         0x00000007
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x3) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x3)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF9FF
+#define     V_03C000_SQ_TEX_XY_FILTER_POINT            0x00000000
+#define     V_03C000_SQ_TEX_XY_FILTER_BILINEAR         0x00000001
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x3) << 11)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 11) & 0x3)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFFE7FF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 13)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 13) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFF9FFF
+#define     V_03C000_SQ_TEX_Z_FILTER_NONE              0x00000000
+#define     V_03C000_SQ_TEX_Z_FILTER_POINT             0x00000001
+#define     V_03C000_SQ_TEX_Z_FILTER_LINEAR            0x00000002
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 15)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 15) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFFE7FFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 20)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 20) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFFCFFFFF
+#define     V_03C000_SQ_TEX_BORDER_COLOR_TRANS_BLACK   0x00000000
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK  0x00000001
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE  0x00000002
+#define     V_03C000_SQ_TEX_BORDER_COLOR_REGISTER      0x00000003
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 22)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 22) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xFE3FFFFF
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER        0x00000000
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESS         0x00000001
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL        0x00000002
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL    0x00000003
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER      0x00000004
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL     0x00000005
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x00000006
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS       0x00000007
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 25)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 25) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0xF9FFFFFF
+#define     V_03C000_SQ_TEX_CHROMA_KEY_DISABLE         0x00000000
+#define     V_03C000_SQ_TEX_CHROMA_KEY_KILL            0x00000001
+#define     V_03C000_SQ_TEX_CHROMA_KEY_BLEND           0x00000002
+
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0xFFF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0xFFF)
+#define   C_03C004_MIN_LOD                             0xFFFFF000
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0xFFF) << 12)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 12) & 0xFFF)
+#define   C_03C004_MAX_LOD                             0xFF000FFF
+
+#define   S_03C004_PERF_MIP(x)                         (((x) & 0xF) << 24)
+#define   G_03C004_PERF_MIP(x)                         (((x) >> 24) & 0xF)
+#define   C_03C004_PERF_MIP                            0xF0FFFFFF
+#define   S_03C004_PERF_Z(x)                           (((x) & 0xF) << 28)
+#define   G_03C004_PERF_Z(x)                           (((x) >> 24) & 0xF)
+#define   C_03C004_PERF_Z                              0x0FFFFFFF
+
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS(x)                         (((x) & 0x3FFF) << 0)
+#define   G_03C008_LOD_BIAS(x)                         (((x) >> 0) & 0x3FFF)
+#define   C_03C008_LOD_BIAS                            0xFFFFC000
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0x3F) << 14)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 14) & 0x3F)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFF03FFF
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 20)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 20) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFEFFFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 21)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 21) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFDFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define     V_008958_DI_PT_NONE                        0x00000000
+#define     V_008958_DI_PT_POINTLIST                   0x00000001
+#define     V_008958_DI_PT_LINELIST                    0x00000002
+#define     V_008958_DI_PT_LINESTRIP                   0x00000003
+#define     V_008958_DI_PT_TRILIST                     0x00000004
+#define     V_008958_DI_PT_TRIFAN                      0x00000005
+#define     V_008958_DI_PT_TRISTRIP                    0x00000006
+#define     V_008958_DI_PT_UNUSED_0                    0x00000007
+#define     V_008958_DI_PT_UNUSED_1                    0x00000008
+#define     V_008958_DI_PT_UNUSED_2                    0x00000009
+#define     V_008958_DI_PT_LINELIST_ADJ                0x0000000A
+#define     V_008958_DI_PT_LINESTRIP_ADJ               0x0000000B
+#define     V_008958_DI_PT_TRILIST_ADJ                 0x0000000C
+#define     V_008958_DI_PT_TRISTRIP_ADJ                0x0000000D
+#define     V_008958_DI_PT_UNUSED_3                    0x0000000E
+#define     V_008958_DI_PT_UNUSED_4                    0x0000000F
+#define     V_008958_DI_PT_TRI_WITH_WFLAGS             0x00000010
+#define     V_008958_DI_PT_RECTLIST                    0x00000011
+#define     V_008958_DI_PT_LINELOOP                    0x00000012
+#define     V_008958_DI_PT_QUADLIST                    0x00000013
+#define     V_008958_DI_PT_QUADSTRIP                   0x00000014
+#define     V_008958_DI_PT_POLYGON                     0x00000015
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V0        0x00000016
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V1        0x00000017
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V2        0x00000018
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V3        0x00000019
+#define     V_008958_DI_PT_2D_FILL_RECT_LIST           0x0000001A
+#define     V_008958_DI_PT_2D_LINE_STRIP               0x0000001B
+#define     V_008958_DI_PT_2D_TRI_STRIP                0x0000001C
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define   S_02881C_CLIP_DIST_ENA_0(x)                  (((x) & 0x1) << 0)
+#define   G_02881C_CLIP_DIST_ENA_0(x)                  (((x) >> 0) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_0                     0xFFFFFFFE
+#define   S_02881C_CLIP_DIST_ENA_1(x)                  (((x) & 0x1) << 1)
+#define   G_02881C_CLIP_DIST_ENA_1(x)                  (((x) >> 1) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_1                     0xFFFFFFFD
+#define   S_02881C_CLIP_DIST_ENA_2(x)                  (((x) & 0x1) << 2)
+#define   G_02881C_CLIP_DIST_ENA_2(x)                  (((x) >> 2) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_2                     0xFFFFFFFB
+#define   S_02881C_CLIP_DIST_ENA_3(x)                  (((x) & 0x1) << 3)
+#define   G_02881C_CLIP_DIST_ENA_3(x)                  (((x) >> 3) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_3                     0xFFFFFFF7
+#define   S_02881C_CLIP_DIST_ENA_4(x)                  (((x) & 0x1) << 4)
+#define   G_02881C_CLIP_DIST_ENA_4(x)                  (((x) >> 4) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_4                     0xFFFFFFEF
+#define   S_02881C_CLIP_DIST_ENA_5(x)                  (((x) & 0x1) << 5)
+#define   G_02881C_CLIP_DIST_ENA_5(x)                  (((x) >> 5) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_5                     0xFFFFFFDF
+#define   S_02881C_CLIP_DIST_ENA_6(x)                  (((x) & 0x1) << 6)
+#define   G_02881C_CLIP_DIST_ENA_6(x)                  (((x) >> 6) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_6                     0xFFFFFFBF
+#define   S_02881C_CLIP_DIST_ENA_7(x)                  (((x) & 0x1) << 7)
+#define   G_02881C_CLIP_DIST_ENA_7(x)                  (((x) >> 7) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_7                     0xFFFFFF7F
+#define   S_02881C_CULL_DIST_ENA_0(x)                  (((x) & 0x1) << 8)
+#define   G_02881C_CULL_DIST_ENA_0(x)                  (((x) >> 8) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_0                     0xFFFFFEFF
+#define   S_02881C_CULL_DIST_ENA_1(x)                  (((x) & 0x1) << 9)
+#define   G_02881C_CULL_DIST_ENA_1(x)                  (((x) >> 9) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_1                     0xFFFFFDFF
+#define   S_02881C_CULL_DIST_ENA_2(x)                  (((x) & 0x1) << 10)
+#define   G_02881C_CULL_DIST_ENA_2(x)                  (((x) >> 10) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_2                     0xFFFFFBFF
+#define   S_02881C_CULL_DIST_ENA_3(x)                  (((x) & 0x1) << 11)
+#define   G_02881C_CULL_DIST_ENA_3(x)                  (((x) >> 11) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_3                     0xFFFFF7FF
+#define   S_02881C_CULL_DIST_ENA_4(x)                  (((x) & 0x1) << 12)
+#define   G_02881C_CULL_DIST_ENA_4(x)                  (((x) >> 12) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_4                     0xFFFFEFFF
+#define   S_02881C_CULL_DIST_ENA_5(x)                  (((x) & 0x1) << 13)
+#define   G_02881C_CULL_DIST_ENA_5(x)                  (((x) >> 13) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_5                     0xFFFFDFFF
+#define   S_02881C_CULL_DIST_ENA_6(x)                  (((x) & 0x1) << 14)
+#define   G_02881C_CULL_DIST_ENA_6(x)                  (((x) >> 14) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_6                     0xFFFFBFFF
+#define   S_02881C_CULL_DIST_ENA_7(x)                  (((x) & 0x1) << 15)
+#define   G_02881C_CULL_DIST_ENA_7(x)                  (((x) >> 15) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_7                     0xFFFF7FFF
+#define   S_02881C_USE_VTX_POINT_SIZE(x)               (((x) & 0x1) << 16)
+#define   G_02881C_USE_VTX_POINT_SIZE(x)               (((x) >> 16) & 0x1)
+#define   C_02881C_USE_VTX_POINT_SIZE                  0xFFFEFFFF
+#define   S_02881C_USE_VTX_EDGE_FLAG(x)                (((x) & 0x1) << 17)
+#define   G_02881C_USE_VTX_EDGE_FLAG(x)                (((x) >> 17) & 0x1)
+#define   C_02881C_USE_VTX_EDGE_FLAG                   0xFFFDFFFF
+#define   S_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) & 0x1) << 18)
+#define   G_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) >> 18) & 0x1)
+#define   C_02881C_USE_VTX_RENDER_TARGET_INDX          0xFFFBFFFF
+#define   S_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) & 0x1) << 19)
+#define   G_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) >> 19) & 0x1)
+#define   C_02881C_USE_VTX_VIEWPORT_INDX               0xFFF7FFFF
+#define   S_02881C_USE_VTX_KILL_FLAG(x)                (((x) & 0x1) << 20)
+#define   G_02881C_USE_VTX_KILL_FLAG(x)                (((x) >> 20) & 0x1)
+#define   C_02881C_USE_VTX_KILL_FLAG                   0xFFEFFFFF
+#define   S_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) & 0x1) << 21)
+#define   G_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) >> 21) & 0x1)
+#define   C_02881C_VS_OUT_MISC_VEC_ENA                 0xFFDFFFFF
+#define   S_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) & 0x1) << 22)
+#define   G_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) >> 22) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST0_VEC_ENA              0xFFBFFFFF
+#define   S_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) & 0x1) << 23)
+#define   G_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) >> 23) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST1_VEC_ENA              0xFF7FFFFF
+/* diff */
+#define R_028860_SQ_PGM_RESOURCES_VS                 0x028860
+#define   S_028860_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_028860_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_028860_NUM_GPRS                            0xFFFFFF00
+#define   S_028860_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_028860_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_028860_STACK_SIZE                          0xFFFF00FF
+#define   S_028860_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_028860_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_028860_DX10_CLAMP                          0xFFDFFFFF
+#define   S_028860_UNCACHED_FIRST_INST(x)              (((x) & 0x1) << 28)
+#define   G_028860_UNCACHED_FIRST_INST(x)              (((x) >> 28) & 0x1)
+#define   C_028860_UNCACHED_FIRST_INST                 0xEFFFFFFF
+#define R_028864_SQ_PGM_RESOURCES_2_VS               0x028864
+
+#define R_028844_SQ_PGM_RESOURCES_PS                 0x028844
+#define   S_028844_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_028844_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_028844_NUM_GPRS                            0xFFFFFF00
+#define   S_028844_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_028844_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_028844_STACK_SIZE                          0xFFFF00FF
+#define   S_028844_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_028844_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_028844_DX10_CLAMP                          0xFFDFFFFF
+#define   S_028844_PRIME_CACHE_ON_DRAW(x)              (((x) & 0x1) << 23)
+#define   G_028844_PRIME_CACHE_ON_DRAW(x)              (((x) >> 23) & 0x1)
+
+#define   S_028844_UNCACHED_FIRST_INST(x)              (((x) & 0x1) << 28)
+#define   G_028844_UNCACHED_FIRST_INST(x)              (((x) >> 28) & 0x1)
+#define   C_028844_UNCACHED_FIRST_INST                 0xEFFFFFFF
+#define   S_028844_CLAMP_CONSTS(x)                     (((x) & 0x1) << 31)
+#define   G_028844_CLAMP_CONSTS(x)                     (((x) >> 31) & 0x1)
+#define   C_028844_CLAMP_CONSTS                        0x7FFFFFFF
+#define R_028848_SQ_PGM_RESOURCES_2_PS                 0x028848
+
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define   S_028644_SEMANTIC(x)                         (((x) & 0xFF) << 0)
+#define   G_028644_SEMANTIC(x)                         (((x) >> 0) & 0xFF)
+#define   C_028644_SEMANTIC                            0xFFFFFF00
+#define   S_028644_DEFAULT_VAL(x)                      (((x) & 0x3) << 8)
+#define   G_028644_DEFAULT_VAL(x)                      (((x) >> 8) & 0x3)
+#define   C_028644_DEFAULT_VAL                         0xFFFFFCFF
+#define   S_028644_FLAT_SHADE(x)                       (((x) & 0x1) << 10)
+#define   G_028644_FLAT_SHADE(x)                       (((x) >> 10) & 0x1)
+#define   C_028644_FLAT_SHADE                          0xFFFFFBFF
+#define   S_028644_SEL_CENTROID(x)                     (((x) & 0x1) << 11)
+#define   G_028644_SEL_CENTROID(x)                     (((x) >> 11) & 0x1)
+#define   C_028644_SEL_CENTROID                        0xFFFFF7FF
+#define   S_028644_SEL_LINEAR(x)                       (((x) & 0x1) << 12)
+#define   G_028644_SEL_LINEAR(x)                       (((x) >> 12) & 0x1)
+#define   C_028644_SEL_LINEAR                          0xFFFFEFFF
+#define   S_028644_CYL_WRAP(x)                         (((x) & 0xF) << 13)
+#define   G_028644_CYL_WRAP(x)                         (((x) >> 13) & 0xF)
+#define   C_028644_CYL_WRAP                            0xFFFE1FFF
+#define   S_028644_PT_SPRITE_TEX(x)                    (((x) & 0x1) << 17)
+#define   G_028644_PT_SPRITE_TEX(x)                    (((x) >> 17) & 0x1)
+#define   C_028644_PT_SPRITE_TEX                       0xFFFDFFFF
+#define   S_028644_SEL_SAMPLE(x)                       (((x) & 0x1) << 18)
+#define   G_028644_SEL_SAMPLE(x)                       (((x) >> 18) & 0x1)
+#define   C_028644_SEL_SAMPLE                          0xFFFBFFFF
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define   S_0286D4_FLAT_SHADE_ENA(x)                   (((x) & 0x1) << 0)
+#define   G_0286D4_FLAT_SHADE_ENA(x)                   (((x) >> 0) & 0x1)
+#define   C_0286D4_FLAT_SHADE_ENA                      0xFFFFFFFE
+#define   S_0286D4_PNT_SPRITE_ENA(x)                   (((x) & 0x1) << 1)
+#define   G_0286D4_PNT_SPRITE_ENA(x)                   (((x) >> 1) & 0x1)
+#define   C_0286D4_PNT_SPRITE_ENA                      0xFFFFFFFD
+#define   S_0286D4_PNT_SPRITE_OVRD_X(x)                (((x) & 0x7) << 2)
+#define   G_0286D4_PNT_SPRITE_OVRD_X(x)                (((x) >> 2) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_X                   0xFFFFFFE3
+#define   S_0286D4_PNT_SPRITE_OVRD_Y(x)                (((x) & 0x7) << 5)
+#define   G_0286D4_PNT_SPRITE_OVRD_Y(x)                (((x) >> 5) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_Y                   0xFFFFFF1F
+#define   S_0286D4_PNT_SPRITE_OVRD_Z(x)                (((x) & 0x7) << 8)
+#define   G_0286D4_PNT_SPRITE_OVRD_Z(x)                (((x) >> 8) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_Z                   0xFFFFF8FF
+#define   S_0286D4_PNT_SPRITE_OVRD_W(x)                (((x) & 0x7) << 11)
+#define   G_0286D4_PNT_SPRITE_OVRD_W(x)                (((x) >> 11) & 0x7)
+#define   C_0286D4_PNT_SPRITE_OVRD_W                   0xFFFFC7FF
+#define   S_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) & 0x1) << 14)
+#define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
+#define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
+
+#define SQ_TEX_INST_LD 0x03
+#define SQ_TEX_INST_GET_GRADIENTS_H 0x7
+#define SQ_TEX_INST_GET_GRADIENTS_V 0x8
+
+#define SQ_TEX_INST_SAMPLE 0x10
+#define SQ_TEX_INST_SAMPLE_L 0x11
+#define SQ_TEX_INST_SAMPLE_C 0x18
+#endif
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 0ed177c66bd..4664105263a 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -146,6 +146,13 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
 	case CHIP_RV740:
 		bc->chiprev = 1;
 		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		bc->chiprev = 2;
+		break;
 	default:
 		R600_ERR("unknown family %d\n", bc->family);
 		return -EINVAL;
@@ -345,6 +352,10 @@ static int check_scalar(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
 	unsigned swizzle_key;
 
+	if (alu->bank_swizzle_force) {
+		alu->bank_swizzle = alu->bank_swizzle_force;
+		return;
+	}
 	swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + 
 		(is_const(alu->src[1].sel) ? 2 : 0 ) + 
 		(is_const(alu->src[2].sel) ? 1 : 0 );
@@ -357,6 +368,10 @@ static int check_vector(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
 	unsigned swizzle_key;
 
+	if (alu->bank_swizzle_force) {
+		alu->bank_swizzle = alu->bank_swizzle_force;
+		return;
+	}
 	swizzle_key = (is_const(alu->src[0].sel) ? 4 : 0 ) + 
 		(is_const(alu->src[1].sel) ? 2 : 0 ) + 
 		(is_const(alu->src[2].sel) ? 1 : 0 );
@@ -462,7 +477,7 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 
 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 {
-	return r600_bc_add_alu_type(bc, alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU);
+	return r600_bc_add_alu_type(bc, alu, BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
 }
 
 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
@@ -475,6 +490,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
 		return 0;
 	}
+	/* all same on EG */
 	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
 	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
 	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
@@ -484,6 +500,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
 		return 0;
 	}
+	/* same on EG */
 	if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
 	     (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
 		LIST_IS_EMPTY(&bc->cf_last->alu)) {
@@ -566,6 +583,7 @@ int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
 	return 0;
 }
 
+/* common to all 3 families */
 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
 {
 	bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
@@ -583,6 +601,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
 	return 0;
 }
 
+/* common to all 3 families */
 static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsigned id)
 {
 	bc->bytecode[id++] = S_SQ_TEX_WORD0_TEX_INST(tex->inst) |
@@ -612,6 +631,7 @@ static int r600_bc_tex_build(struct r600_bc *bc, struct r600_bc_tex *tex, unsign
 	return 0;
 }
 
+/* r600 only, r700/eg bits in r700_asm.c */
 static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {
 	unsigned i;
@@ -662,6 +682,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 	return 0;
 }
 
+/* common for r600/r700 - eg in eg_asm.c */
 static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 {
 	unsigned id = cf->id;
@@ -748,6 +769,8 @@ int r600_bc_build(struct r600_bc *bc)
 			break;
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+		case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+		case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
 			break;
 		case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
 		case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
@@ -771,7 +794,10 @@ int r600_bc_build(struct r600_bc *bc)
 		return -ENOMEM;
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
 		addr = cf->addr;
-		r = r600_bc_cf_build(bc, cf);
+		if (bc->chiprev == 2)
+			r = eg_bc_cf_build(bc, cf);
+		else
+			r = r600_bc_cf_build(bc, cf);
 		if (r)
 			return r;
 		switch (cf->inst) {
@@ -783,6 +809,7 @@ int r600_bc_build(struct r600_bc *bc)
 					r = r600_bc_alu_build(bc, alu, addr);
 					break;
 				case 1:
+				case 2: /* eg alu is same encoding as r700 */
 					r = r700_bc_alu_build(bc, alu, addr);
 					break;
 				default:
@@ -816,6 +843,8 @@ int r600_bc_build(struct r600_bc *bc)
 			break;
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+		case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+		case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
 		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
 		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
 		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index d4b3463af59..cc62535e5cd 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -57,6 +57,7 @@ struct r600_bc_alu {
 	unsigned			nliteral;
 	unsigned			literal_added;
 	unsigned                        bank_swizzle;
+  	unsigned                        bank_swizzle_force;
 	u32				value[4];
 	int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
 };
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index ed8f2655fba..80573a638b7 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -34,7 +34,6 @@
 #include "r600_resource.h"
 #include "r600d.h"
 
-
 static void r600_destroy_context(struct pipe_context *context)
 {
 	struct r600_context *rctx = r600_context(context);
@@ -115,7 +114,10 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 	rctx->screen = rscreen;
 	rctx->rw = rscreen->rw;
 
-	rctx->vtbl = &r600_hw_state_vtbl;
+	if (rscreen->chip_class == EVERGREEN)
+		rctx->vtbl = &eg_hw_state_vtbl;
+	else
+		rctx->vtbl = &r600_hw_state_vtbl;
 
 	r600_init_blit_functions(rctx);
 	r600_init_query_functions(rctx);
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 76a05f81fc5..58f6d0232b0 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -175,6 +175,7 @@ struct r600_context_hw_state_vtbl {
 	void (*init_config)(struct r600_context *rctx);
 };
 extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
+extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;
 
 struct r600_context {
 	struct pipe_context		context;
@@ -185,6 +186,7 @@ struct r600_context {
 	struct radeon_draw		draw;
 	struct r600_context_hw_state_vtbl *vtbl;
 	struct radeon_state		config;
+	boolean use_mem_constant;
 	/* FIXME get rid of those vs_resource,vs/ps_constant */
 	struct radeon_state		*vs_resource;
 	unsigned			vs_nresource;
@@ -263,11 +265,16 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 extern void r600_queries_resume(struct pipe_context *ctx);
 extern void r600_queries_suspend(struct pipe_context *ctx);
 
+int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
+
 void r600_set_constant_buffer_file(struct pipe_context *ctx,
 				   uint shader, uint index,
 				   struct pipe_resource *buffer);
 void r600_set_constant_buffer_mem(struct pipe_context *ctx,
 				  uint shader, uint index,
 				  struct pipe_resource *buffer);
+void eg_set_constant_buffer(struct pipe_context *ctx,
+			    uint shader, uint index,
+			    struct pipe_resource *buffer);
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index 4de3eae065f..3d3e87d7234 100644
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -25,6 +25,7 @@
  *      Jerome Glisse
  *      Dave Airlie
  */
+
 #include <util/u_inlines.h>
 #include <util/u_format.h>
 #include <util/u_memory.h>
diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h
index ae3d46e2e51..0cf9c1c401c 100644
--- a/src/gallium/drivers/r600/r600_opcodes.h
+++ b/src/gallium/drivers/r600/r600_opcodes.h
@@ -171,8 +171,226 @@
 #define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000027
 #define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000028
 
-#define BC_INST(bc, x) (x)
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_NOP                             0x00000000
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX                             0x00000001
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX                             0x00000002
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_GDS                             0x00000003
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START                      0x00000004
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END                        0x00000005
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10                 0x00000006
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL                0x00000007
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE                   0x00000008
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK                      0x00000009
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP                            0x0000000A
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_PUSH                            0x0000000B
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_12                                     0x0000000C /* resvd */
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE                            0x0000000D
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_POP                             0x0000000E
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_15                                     0x0000000F
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_16                                     0x00000010
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_17                                     0x00000011
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL                            0x00000012
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS                         0x00000013
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN                          0x00000014
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_VERTEX                     0x00000015
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_EMIT_CUT_VERTEX                 0x00000016
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_CUT_VERTEX                      0x00000017
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_KILL                            0x00000018
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_RSVD_25                                     0x00000019
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_WAIT_ACK                        0x0000001a
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_TC_ACK                          0x0000001b
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_VC_ACK                          0x0000001c
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMPTABLE                       0x0000001d
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_GLOBAL_WAVE_SYNC                0x0000001e
+#define     EG_V_SQ_CF_WORD1_SQ_CF_INST_HALT                            0x0000001f
 
-#define CTX_INST(x) (x)
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU                         0x00000008
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE             0x00000009
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER               0x0000000A
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER              0x0000000B
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_EXTENDED                    0x0000000C
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_CONTINUE                0x0000000D
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_BREAK                   0x0000000E
+#define     EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_ELSE_AFTER              0x0000000F
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD                       0x00000000
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL                       0x00000001
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE                  0x00000002
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX                       0x00000003
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN                       0x00000004
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_DX10                  0x00000005
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_DX10                  0x00000006
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE                      0x00000008
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT                     0x00000009
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE                     0x0000000A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE                     0x0000000B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_DX10                 0x0000000C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_DX10                0x0000000D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_DX10                0x0000000E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_DX10                0x0000000F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT                     0x00000010
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC                     0x00000011
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL                      0x00000012
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE                     0x00000013
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR                     0x00000014
+/* same up to here */
+/*
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA                      0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR                0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT                  0x00000018
+*/
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT                  0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT                  0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT                  0x00000017
+/* same again from here */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV                       0x00000019
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP                       0x0000001A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64                    0x0000001B /* new EG */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT64_TO_FLT32            0x0000001C /* new EG */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64            0x0000001D /* new EG */
+/* same */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_UINT           0x0000001E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_UINT           0x0000001F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE                 0x00000020
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT                0x00000021
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE                0x00000022
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE                0x00000023
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_INV              0x00000024
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_POP              0x00000025
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_CLR              0x00000026
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SET_RESTORE          0x00000027
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH            0x00000028
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH           0x00000029
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH           0x0000002A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH           0x0000002B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE                     0x0000002C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT                    0x0000002D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE                    0x0000002E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE                    0x0000002F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT                   0x00000030
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT                    0x00000031
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT                   0x00000032
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT                   0x00000033
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT                   0x00000034
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT                   0x00000035
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT                   0x00000036
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT                   0x00000037
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT                  0x00000038
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT                  0x00000039
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT                  0x0000003A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT                 0x0000003B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT                 0x0000003C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT                 0x0000003D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT                0x0000003E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT                0x0000003F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_UINT               0x00000040
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_UINT               0x00000041
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT             0x00000042
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_INT            0x00000043
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_INT            0x00000044
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT            0x00000045
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE_INT                 0x00000046
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT_INT                0x00000047
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE_INT                0x00000048
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE_INT                0x00000049
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_PUSH_INT        0x0000004A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT_PUSH_INT       0x0000004B
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_PUSH_INT       0x0000004C
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT       0x0000004D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT       0x0000004E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT       0x0000004F
+/* same up to here */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT                0x00000050
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFREV_INT                 0x00000051
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADDC_UINT                 0x00000052
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUBB_UINT                 0x00000053
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_BARRIER             0x00000054
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_BEGIN           0x00000055
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_GROUP_SEQ_END             0x00000056
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_MODE                  0x00000057
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX0               0x00000058
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_CF_IDX1               0x00000059
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SET_LDS_SIZE              0x0000005A
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE                  0x00000081
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED               0x00000082
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE                  0x00000083
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED             0x00000084
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF                  0x00000085
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE                0x00000086
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED         0x00000087
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF              0x00000088
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE            0x00000089
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE                 0x0000008A
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN                       0x0000008D
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS                       0x0000008E
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT                 0x0000008F
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT                 0x00000090
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT                0x00000091
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT                0x00000092
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT                 0x00000093
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT                0x00000094
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_64                  0x00000095
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED_64          0x00000096
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_64              0x00000097
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED_64      0x00000098
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_64                   0x00000099
+/* TODO Fill in more ALU */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4                      0x000000BE
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE                 0x000000BF
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE                      0x000000C0
+
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY                      0x000000D6
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW                      0x000000D7
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_X                       0x000000D8
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_Z                       0x000000D9
+
+
+/* TODO ADD OTHER OP3 */
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD                    0x00000014
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M2                 0x00000015
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_M4                 0x00000016
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_D2                 0x00000017
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_IEEE               0x00000018
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE                      0x00000019
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT                     0x0000001A
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE                     0x0000001B
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT                  0x0000001C
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT                 0x0000001D
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT                 0x0000001E
+#define     EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT                   0x0000001F
+
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0   0x00000040
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1   0x00000041
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2   0x00000042
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3   0x00000043
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0   0x00000044
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1   0x00000045
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2   0x00000046
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3   0x00000047
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0   0x00000048
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1   0x00000049
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2   0x0000004A
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3   0x0000004B
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0   0x0000004C
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1   0x0000004D
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2   0x0000004E
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3   0x0000004F
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH        0x00000050
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING           0x00000052
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000053
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000054
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT         0x00000055
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT            0x00000056
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_CACHELESS  0x00000057
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING1          0x00000058
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING2          0x00000059
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING3          0x0000005A
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED 0x0000005B
+#define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS  0x0000005C
+
+#define BC_INST(bc, x) ((bc)->chiprev == 2 ? EG_##x : x)
+
+#define CTX_INST(x) (ctx->bc->chiprev == 2 ? EG_##x : x)
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index 54a61ddfb33..bb215a33670 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -46,8 +46,10 @@ static const char* r600_get_name(struct pipe_screen* pscreen)
 
 	if (family >= CHIP_R600 && family < CHIP_RV770)
 		return "R600 (HD2XXX,HD3XXX)";
-	else
+	else if (family < CHIP_CEDAR)
 		return "R700 (HD4XXX)";
+	else
+		return "EVERGREEN";
 }
 
 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
@@ -261,6 +263,14 @@ struct pipe_screen *r600_screen_create(struct radeon *rw)
 	case CHIP_RV740:
 		rscreen->chip_class = R700;
 		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		rscreen->chip_class = EVERGREEN;
+		rscreen->use_mem_constant = TRUE;
+		break;
 	default:
 		FREE(rscreen);
 		return NULL;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 129c95ef68a..2a0f7b3056c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -61,7 +61,7 @@ struct r600_shader_tgsi_instruction {
 	int (*process)(struct r600_shader_ctx *ctx);
 };
 
-static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
+static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
 
@@ -242,6 +242,39 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
+{
+	int i, r;
+	struct r600_bc_alu alu;
+
+	for (i = 0; i < 8; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		if (i < 4)
+			alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
+		else
+			alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
+
+		if ((i > 1) && (i < 6)) {
+			alu.dst.sel = ctx->shader->input[gpr].gpr;
+			alu.dst.write = 1;
+		}
+
+		alu.dst.chan = i % 4;
+		alu.src[0].chan = (1 - (i % 2));
+		alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
+
+		alu.bank_swizzle_force = SQ_ALU_VEC_210;
+		if ((i % 4) == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}	
+		
+			
 static int tgsi_declaration(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
@@ -275,6 +308,10 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 			if (r)
 				return r;
 		}
+		if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
+			/* turn input into interpolate on EG */
+			evergreen_interp_alu(ctx, i);
+		}
 		break;
 	case TGSI_FILE_OUTPUT:
 		i = ctx->shader->noutput++;
@@ -391,7 +428,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			/* reserve first tmp for everyone */
 			r600_get_temp(&ctx);
 			opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
-			ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
+			if (ctx.bc->chiprev == 2)
+				ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
+			else
+				ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
 			r = ctx.inst_info->process(&ctx);
 			if (r)
 				goto out_err;
@@ -2161,6 +2201,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 	return tgsi_helper_copy(ctx, inst);
 }
 
+/* r6/7 only for now */
 static int tgsi_arl(struct r600_shader_ctx *ctx)
 {
 	/* TODO from r600c, ar values don't persist between clauses */
@@ -2658,3 +2699,161 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ENDSWITCH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_LAST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 };
+
+static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
+	{TGSI_OPCODE_ARL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MOV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
+	{TGSI_OPCODE_LIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
+	{TGSI_OPCODE_RCP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_RSQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_EXP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
+	{TGSI_OPCODE_LOG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
+	{TGSI_OPCODE_ADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
+	{TGSI_OPCODE_DP3,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DP4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+	{TGSI_OPCODE_DST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
+	{TGSI_OPCODE_MIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
+	{TGSI_OPCODE_MAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
+	{TGSI_OPCODE_SLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
+	{TGSI_OPCODE_SGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
+	{TGSI_OPCODE_MAD,	1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
+	{TGSI_OPCODE_SUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
+	{TGSI_OPCODE_LRP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
+	{TGSI_OPCODE_CND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	/* gap */
+	{20,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2A,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	/* gap */
+	{22,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{23,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FRC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
+	{TGSI_OPCODE_CLAMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FLR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
+	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_EX2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_LG2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_POW,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
+	{TGSI_OPCODE_XPD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
+	/* gap */
+	{32,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
+	{TGSI_OPCODE_RCC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DPH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+	{TGSI_OPCODE_COS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
+	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
+	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
+	{TGSI_OPCODE_KILP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
+	{TGSI_OPCODE_PK2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PK4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
+	{TGSI_OPCODE_SFL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
+	{TGSI_OPCODE_SIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
+	{TGSI_OPCODE_SLE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
+	{TGSI_OPCODE_SNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
+	{TGSI_OPCODE_STR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_TXD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXP,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
+	{TGSI_OPCODE_UP2H,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP2US,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4B,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UP4UB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_X2D,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BRA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CAL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_RET,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SSG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
+	{TGSI_OPCODE_CMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
+	{TGSI_OPCODE_SCS,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
+	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
+	{TGSI_OPCODE_NRM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DP2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
+	{TGSI_OPCODE_TXL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BRK,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_IF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
+	/* gap */
+	{75,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{76,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ELSE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
+	{TGSI_OPCODE_ENDIF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
+	/* gap */
+	{79,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{80,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_PUSHA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_POPA,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CEIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_I2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NOT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TRUNC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_SHL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	/* gap */
+	{88,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_AND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_OR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_XOR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CONT,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
+	{TGSI_OPCODE_EMIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDPRIM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BGNLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
+	{TGSI_OPCODE_BGNSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDLOOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
+	{TGSI_OPCODE_ENDSUB,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	/* gap */
+	{103,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{104,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{105,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{106,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NOP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	/* gap */
+	{108,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{109,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{110,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{111,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_NRM4,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CALLNZ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IFC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BREAKC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_KIL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
+	{TGSI_OPCODE_END,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
+	/* gap */
+	{118,			0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_F2I,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_INEG,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ISGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ISHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ISLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_F2U,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_U2F,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UADD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UDIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UMAD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UMAX,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UMIN,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UMOD,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_UMUL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_USEQ,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_USGE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_USHR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_USLT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_USNE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CASE,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DEFAULT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDSWITCH,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LAST,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+};
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index d0f5726d251..0573e63dc82 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -135,15 +135,7 @@
 #define   S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) & 0x7F) << 23)
 #define   G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(x)                      (((x) >> 23) & 0x7F)
 #define   C_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST                         0xC07FFFFF
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0        0x00000020
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1        0x00000021
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2        0x00000022
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3        0x00000023
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_SCRATCH        0x00000024
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_REDUCTION      0x00000025
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RING           0x00000026
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT             0x00000027
-#define     V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE        0x00000028
+
 #define   S_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x)              (((x) & 0x1) << 30)
 #define   G_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE(x)              (((x) >> 30) & 0x1)
 #define   C_SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE                 0xBFFFFFFF
@@ -187,6 +179,7 @@
  * 253  SQ_ALU_SRC_LITERAL: literal constant.
  * 254  SQ_ALU_SRC_PV: previous vector result.
  * 255  SQ_ALU_SRC_PS: previous scalar result.
+ * 448  EG - INTERP SRC BASE
  */
 #define     V_SQ_ALU_SRC_0                                           0x000000F8
 #define     V_SQ_ALU_SRC_1                                           0x000000F9
@@ -194,6 +187,7 @@
 #define     V_SQ_ALU_SRC_M_1_INT                                     0x000000FB
 #define     V_SQ_ALU_SRC_0_5                                         0x000000FC
 #define     V_SQ_ALU_SRC_LITERAL                                     0x000000FD
+#define     V_SQ_ALU_SRC_PARAM_BASE                                  0x000001C0
 #define   S_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) & 0x1) << 9)
 #define   G_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) >> 9) & 0x1)
 #define   C_SQ_ALU_WORD0_SRC0_REL                                    0xFFFFFDFF
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 28c686a494c..9203f4408c1 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -509,10 +509,14 @@ void r600_init_state_functions(struct r600_context *rctx)
 	rctx->context.delete_vs_state = r600_delete_state;
 	rctx->context.set_blend_color = r600_set_blend_color;
 	rctx->context.set_clip_state = r600_set_clip_state;
-	if (rctx->screen->use_mem_constant)
+
+	if (rctx->screen->chip_class == EVERGREEN)
+		rctx->context.set_constant_buffer = eg_set_constant_buffer;
+	else if (rctx->screen->use_mem_constant)
 		rctx->context.set_constant_buffer = r600_set_constant_buffer_mem;
 	else
 		rctx->context.set_constant_buffer = r600_set_constant_buffer_file;
+
 	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
 	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
 	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
@@ -625,7 +629,6 @@ static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
 	struct pipe_surface *surf;
-	int i;
 
 	surf = rctx->framebuffer->state.framebuffer.zsbuf;
 
@@ -647,7 +650,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	unsigned i;
-
+	
 	/* build new states */
 	rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer);
 	rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
@@ -659,12 +662,15 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
 
 	/* bind states */
+	radeon_draw_bind(&rctx->draw, &rctx->config);
+
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
 
-	radeon_draw_bind(&rctx->draw, &rctx->config);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
 
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
 	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index b6698e3885c..dec616bce88 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -523,7 +523,7 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 			if (desc->channel[0].size == 5 &&
 			    desc->channel[1].size == 6 &&
 			    desc->channel[2].size == 5) {
-				result |= V_0280A0_COLOR_5_6_5;
+				result = V_0280A0_COLOR_5_6_5;
 				goto out_word4;
 			}
 			goto out_unknown;
@@ -532,14 +532,14 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 			    desc->channel[1].size == 5 &&
 			    desc->channel[2].size == 5 &&
 			    desc->channel[3].size == 1) {
-				result |= V_0280A0_COLOR_1_5_5_5;
+				result = V_0280A0_COLOR_1_5_5_5;
 				goto out_word4;
 			}
 			if (desc->channel[0].size == 10 &&
 			    desc->channel[1].size == 10 &&
 			    desc->channel[2].size == 10 &&
 			    desc->channel[3].size == 2) {
-				result |= V_0280A0_COLOR_10_10_10_2;
+				result = V_0280A0_COLOR_10_10_10_2;
 				goto out_word4;
 			}
 			goto out_unknown;
@@ -560,36 +560,36 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 		case 4:
 			switch (desc->nr_channels) {
 			case 2:
-				result |= V_0280A0_COLOR_4_4;
+				result = V_0280A0_COLOR_4_4;
 				goto out_word4;
 			case 4:
-				result |= V_0280A0_COLOR_4_4_4_4;
+				result = V_0280A0_COLOR_4_4_4_4;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 8:
 			switch (desc->nr_channels) {
 			case 1:
-				result |= V_0280A0_COLOR_8;
+				result = V_0280A0_COLOR_8;
 				goto out_word4;
 			case 2:
-				result |= V_0280A0_COLOR_8_8;
+				result = V_0280A0_COLOR_8_8;
 				goto out_word4;
 			case 4:
-				result |= V_0280A0_COLOR_8_8_8_8;
+				result = V_0280A0_COLOR_8_8_8_8;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 16:
 			switch (desc->nr_channels) {
 			case 1:
-				result |= V_0280A0_COLOR_16;
+				result = V_0280A0_COLOR_16;
 				goto out_word4;
 			case 2:
-				result |= V_0280A0_COLOR_16_16;
+				result = V_0280A0_COLOR_16_16;
 				goto out_word4;
 			case 4:
-				result |= V_0280A0_COLOR_16_16_16_16;
+				result = V_0280A0_COLOR_16_16_16_16;
 				goto out_word4;
 			}
 		}
@@ -600,26 +600,26 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 		case 16:
 			switch (desc->nr_channels) {
 			case 1:
-				result |= V_0280A0_COLOR_16_FLOAT;
+				result = V_0280A0_COLOR_16_FLOAT;
 				goto out_word4;
 			case 2:
-				result |= V_0280A0_COLOR_16_16_FLOAT;
+				result = V_0280A0_COLOR_16_16_FLOAT;
 				goto out_word4;
 			case 4:
-				result |= V_0280A0_COLOR_16_16_16_16_FLOAT;
+				result = V_0280A0_COLOR_16_16_16_16_FLOAT;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 32:
 			switch (desc->nr_channels) {
 			case 1:
-				result |= V_0280A0_COLOR_32_FLOAT;
+				result = V_0280A0_COLOR_32_FLOAT;
 				goto out_word4;
 			case 2:
-				result |= V_0280A0_COLOR_32_32_FLOAT;
+				result = V_0280A0_COLOR_32_32_FLOAT;
 				goto out_word4;
 			case 4:
-				result |= V_0280A0_COLOR_32_32_32_32_FLOAT;
+				result = V_0280A0_COLOR_32_32_32_32_FLOAT;
 				goto out_word4;
 			}
 		}
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index 7f7ce5a4bac..e754d733afc 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -26,6 +26,7 @@
 #include "r700_sq.h"
 #include <stdio.h>
 
+
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {
 	unsigned i;
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 5759f363ead..cd063e4a94c 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -217,6 +217,7 @@ enum r600_stype {
 };
 
 #include "r600_states_inc.h"
+#include "eg_states_inc.h"
 
 /* R600 QUERY BEGIN/END */
 #define R600_QUERY__OFFSET			0
diff --git a/src/gallium/winsys/r600/drm/eg_states.h b/src/gallium/winsys/r600/drm/eg_states.h
new file mode 100644
index 00000000000..0334e633a2b
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/eg_states.h
@@ -0,0 +1,521 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef EG_STATES_H
+#define EG_STATES_H
+
+static const struct radeon_register EG_names_CONFIG[] = {
+	{0x00008C00, 0, 0, "SQ_CONFIG"},
+	{0x00009100, 0, 0, "SPI_CONFIG_CNTL"},
+	{0x0000913C, 0, 0, "SPI_CONFIG_CNTL_1"},
+	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
+	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
+	{0x00008C0C, 0, 0, "SQ_GPR_RESOURCE_MGMT_3"},
+	{0x00008C18, 0, 0, "SQ_THREAD_RESOURCE_MGMT_1"},
+	{0x00008C1C, 0, 0, "SQ_THREAD_RESOURCE_MGMT_2"},
+	{0x00008C20, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
+	{0x00008C24, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
+	{0x00008C28, 0, 0, "SQ_STACK_RESOURCE_MGMT_3"},
+	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
+	{0x00008A14, 0, 0, "PA_CL_ENHANCE"},
+	{0x00028838, 0, 0, "SQ_DYN_GPR_RESOURCE_LIMIT_1"},
+	{0x000288EC, 0, 0, "SQ_LDS_ALLOC_PS"},
+	{0x00028350, 0, 0, "SX_MISC"},
+	{0x00028900, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
+	{0x00028904, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
+	{0x00028908, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
+	{0x0002890C, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
+	{0x00028910, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
+	{0x00028914, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
+	{0x0002891C, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
+	{0x00028920, 0, 0, "SQ_GS_VERT_ITEMSIZE_1"},
+	{0x00028924, 0, 0, "SQ_GS_VERT_ITEMSIZE_2"},
+	{0x00028928, 0, 0, "SQ_GS_VERT_ITEMSIZE_3"},
+	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
+	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
+	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
+	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
+	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
+	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
+	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
+	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
+	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
+	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
+	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
+	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
+	{0x00028A40, 0, 0, "VGT_GS_MODE"},
+	{0x00028A48, 0, 0, "PA_SC_MODE_CNTL_0"},
+	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL_1"},
+	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
+	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
+	{0x00028B54, 0, 0, "VGT_SHADER_STAGES_EN"},
+	{0x00028B94, 0, 0, "VGT_STRMOUT_CONFIG"},
+	{0x00028B98, 0, 0, "VGT_STRMOUT_BUFFER_CONFIG"},
+};
+
+static const struct radeon_register EG_names_CB_CNTL[] = {
+	{0x00028238, 0, 0, "CB_TARGET_MASK"},
+	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
+	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
+	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
+	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
+	{0x00028C3C, 0, 0, "PA_SC_AA_MASK"},
+};
+
+static const struct radeon_register EG_names_RASTERIZER[] = {
+	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
+	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
+	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
+	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
+	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
+	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
+	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
+	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
+	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
+	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
+	{0x00028C08, 0, 0, "PA_SU_VTX_CNTL"},
+	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
+	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
+	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
+	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
+	{0x00028B78, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
+	{0x00028B7C, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
+	{0x00028B80, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
+	{0x00028B84, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
+	{0x00028B88, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
+	{0x00028B8C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
+};
+
+/* Viewport states are same as r600 */
+static const struct radeon_register EG_names_VIEWPORT[] = {
+	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
+	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
+	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
+	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
+	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
+	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
+	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
+	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
+	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
+};
+
+/* scissor is same as R600 */
+static const struct radeon_register EG_names_SCISSOR[] = {
+	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
+	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
+	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
+	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
+	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
+	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
+	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
+	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
+	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
+	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
+	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
+	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
+	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
+	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
+	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
+	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
+	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
+	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
+	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
+	{0x00028234, 0, 0, "PA_SU_HARDWARE_SCREEN_OFFSET"},
+};
+
+/* same as r700 i.e. no blend control */
+static const struct radeon_register EG_names_BLEND[] = {
+	{0x00028414, 0, 0, "CB_BLEND_RED"},
+	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
+	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
+	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
+	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
+	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
+	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
+	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
+	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
+	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
+	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
+	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
+};
+
+/* different */
+static const struct radeon_register EG_names_DSA[] = {
+	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
+	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
+	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
+	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
+	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
+	{0x00028438, 0, 0, "SX_ALPHA_REF"},
+	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
+	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
+	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
+	{0x00028000, 0, 0, "DB_RENDER_CONTROL"},
+	{0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"},
+	{0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"},
+	{0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"},
+	{0x00028AC4, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
+	{0x00028AC8, 0, 0, "DB_PRELOAD_CONTROL"},
+	{0x00028B70, 0, 0, "DB_ALPHA_TO_MASK"},
+};
+
+/* different */
+static const struct radeon_register EG_names_VS_SHADER[] = {
+	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
+	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
+	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
+	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
+	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
+	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
+	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
+	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
+	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
+	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
+	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
+	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
+	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
+	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
+	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
+	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
+	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
+	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
+	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
+	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
+	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
+	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
+	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
+	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
+	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
+	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
+	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
+	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
+	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
+	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
+	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
+	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
+	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_0"}, // all diff belwo
+	{0x00028620, 0, 0, "SPI_VS_OUT_ID_1"},
+	{0x00028624, 0, 0, "SPI_VS_OUT_ID_2"},
+	{0x00028628, 0, 0, "SPI_VS_OUT_ID_3"},
+	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_4"},
+	{0x00028630, 0, 0, "SPI_VS_OUT_ID_5"},
+	{0x00028634, 0, 0, "SPI_VS_OUT_ID_6"},
+	{0x00028638, 0, 0, "SPI_VS_OUT_ID_7"},
+	{0x0002863C, 0, 0, "SPI_VS_OUT_ID_8"},
+	{0x00028640, 0, 0, "SPI_VS_OUT_ID_9"},
+	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
+	{0x0002885C, 1, 0, "SQ_PGM_START_VS"}, 
+	{0x00028860, 0, 0, "SQ_PGM_RESOURCES_VS"},
+	{0x00028864, 0, 0, "SQ_PGM_RESOURCES_2_VS"},
+	{0x000288A4, 1, 1, "SQ_PGM_START_FS"},
+	{0x000288A8, 0, 0, "SQ_PGM_RESOURCES_FS"},
+};
+
+static const struct radeon_register EG_names_PS_SHADER[] = {
+	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
+	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
+	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
+	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
+	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
+	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
+	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
+	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
+	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
+	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
+	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
+	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
+	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
+	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
+	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
+	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
+	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
+	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
+	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
+	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
+	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
+	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
+	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
+	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
+	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
+	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
+	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
+	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
+	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
+	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
+	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
+	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
+	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
+	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
+	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
+	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
+	{0x000286E0, 0, 0, "SPI_BARYC_CNTL"},
+	{0x000286E4, 0, 0, "SPI_PS_IN_CONTROL_2"},
+	{0x000286E8, 0, 0, "SPI_COMPUTE_INPUT_CNTL"},
+	{0x00028840, 1, 0, "SQ_PGM_START_PS"}, // diff
+	{0x00028844, 0, 0, "SQ_PGM_RESOURCES_PS"}, // diff
+	{0x00028848, 0, 0, "SQ_PGM_RESOURCES_2_PS"}, // diff
+	{0x0002884C, 0, 0, "SQ_PGM_EXPORTS_PS"}, // diff
+};
+
+/* different */
+static const struct radeon_register EG_names_UCP[] = {
+	{0x000285BC, 0, 0, "PA_CL_UCP0_X"},
+	{0x000285C0, 0, 0, "PA_CL_UCP0_Y"},
+	{0x000285C4, 0, 0, "PA_CL_UCP0_Z"},
+	{0x000285C8, 0, 0, "PA_CL_UCP0_W"},
+	{0x000285CC, 0, 0, "PA_CL_UCP1_X"},
+	{0x000285D0, 0, 0, "PA_CL_UCP1_Y"},
+	{0x000285D4, 0, 0, "PA_CL_UCP1_Z"},
+	{0x000285D8, 0, 0, "PA_CL_UCP1_W"},
+	{0x000285DC, 0, 0, "PA_CL_UCP2_X"},
+	{0x000285E0, 0, 0, "PA_CL_UCP2_Y"},
+	{0x000285E4, 0, 0, "PA_CL_UCP2_Z"},
+	{0x000285E8, 0, 0, "PA_CL_UCP2_W"},
+	{0x000285EC, 0, 0, "PA_CL_UCP3_X"},
+	{0x000285F0, 0, 0, "PA_CL_UCP3_Y"},
+	{0x000285F4, 0, 0, "PA_CL_UCP3_Z"},
+	{0x000285F8, 0, 0, "PA_CL_UCP3_W"},
+	{0x000285FC, 0, 0, "PA_CL_UCP4_X"},
+	{0x00028600, 0, 0, "PA_CL_UCP4_Y"},
+	{0x00028604, 0, 0, "PA_CL_UCP4_Z"},
+	{0x00028608, 0, 0, "PA_CL_UCP4_W"},
+	{0x0002860C, 0, 0, "PA_CL_UCP5_X"},
+	{0x00028610, 0, 0, "PA_CL_UCP5_Y"},
+	{0x00028614, 0, 0, "PA_CL_UCP5_Z"},
+	{0x0002861C, 0, 0, "PA_CL_UCP5_W"},
+};
+
+static const struct radeon_register EG_names_VS_CBUF[] = {
+	{0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"},
+	{0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"},
+};
+
+static const struct radeon_register EG_names_PS_CBUF[] = {
+	{0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"},
+	{0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"},
+};
+
+static const struct radeon_register EG_names_PS_RESOURCE[] = {
+	{0x00030000, 0, 0, "RESOURCE0_WORD0"},
+	{0x00030004, 0, 0, "RESOURCE0_WORD1"},
+	{0x00030008, 0, 0, "RESOURCE0_WORD2"},
+	{0x0003000C, 0, 0, "RESOURCE0_WORD3"},
+	{0x00030010, 0, 0, "RESOURCE0_WORD4"},
+	{0x00030014, 0, 0, "RESOURCE0_WORD5"},
+	{0x00030018, 0, 0, "RESOURCE0_WORD6"},
+	{0x0003001c, 0, 0, "RESOURCE0_WORD7"},
+};
+
+static const struct radeon_register EG_names_VS_RESOURCE[] = {
+	{0x00031600, 0, 0, "RESOURCE160_WORD0"},
+	{0x00031604, 0, 0, "RESOURCE160_WORD1"},
+	{0x00031608, 0, 0, "RESOURCE160_WORD2"},
+	{0x0003160C, 0, 0, "RESOURCE160_WORD3"},
+	{0x00031610, 0, 0, "RESOURCE160_WORD4"},
+	{0x00031614, 0, 0, "RESOURCE160_WORD5"},
+	{0x00031618, 0, 0, "RESOURCE160_WORD6"},
+	{0x0003161c, 0, 0, "RESOURCE160_WORD7"},
+};
+
+static const struct radeon_register EG_names_FS_RESOURCE[] = {
+	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
+	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
+	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
+	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
+	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
+	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
+	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
+	{0x0003A31C, 0, 0, "RESOURCE320_WORD7"},
+};
+
+static const struct radeon_register EG_names_GS_RESOURCE[] = {
+	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
+	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
+	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
+	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
+	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
+	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
+	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
+	{0x0003A4DC, 0, 0, "RESOURCE336_WORD7"},
+};
+
+static const struct radeon_register EG_names_PS_SAMPLER[] = {
+	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
+	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
+	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
+};
+
+static const struct radeon_register EG_names_VS_SAMPLER[] = {
+	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
+	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
+	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
+};
+
+static const struct radeon_register EG_names_GS_SAMPLER[] = {
+	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
+	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
+	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
+};
+
+static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = {
+	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
+	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = {
+	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
+	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = {
+	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
+	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register EG_names_CB0[] = {
+	{0x00028C60, 1, 0, "CB_COLOR0_BASE"},
+	{0x00028C64, 0, 0, "CB_COLOR0_PITCH"},
+	{0x00028C68, 0, 0, "CB_COLOR0_SLICE"},
+	{0x00028C6C, 0, 0, "CB_COLOR0_VIEW"},
+	{0x00028C70, 1, 0, "CB_COLOR0_INFO"},
+	{0x00028C74, 0, 0, "CB_COLOR0_ATTRIB"},
+	{0x00028C78, 0, 0, "CB_COLOR0_DIM"},
+};
+
+/* TODO */
+static const struct radeon_register EG_names_CB1[] = {
+	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
+	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+	{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+	{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register EG_names_CB2[] = {
+	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
+	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+	{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+	{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register EG_names_CB3[] = {
+	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+	{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+	{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register EG_names_CB4[] = {
+	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
+	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+	{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+	{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register EG_names_CB5[] = {
+	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
+	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+	{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+	{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register EG_names_CB6[] = {
+	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
+	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+	{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+	{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register EG_names_CB7[] = {
+	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+	{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+	{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+/* TODO */
+
+/* different - TODO */
+static const struct radeon_register EG_names_DB[] = {
+	{0x00028014, 1, 0, "DB_HTILE_DATA_BASE"},
+	{0x00028040, 1, 0, "DB_Z_INFO"},
+	{0x00028044, 0, 0, "DB_STENCIL_INFO"},
+	{0x00028058, 0, 0, "DB_DEPTH_SIZE"},
+	{0x0002805C, 0, 0, "DB_DEPTH_SLICE"},
+	{0x00028008, 0, 0, "DB_DEPTH_VIEW"},
+	{0x00028ABC, 0, 0, "DB_HTILE_SURFACE"},
+	{0x00028048, 1, 0, "DB_Z_READ_BASE"},
+	{0x0002804C, 1, 0, "DB_STENCIL_READ_BASE"},
+	{0x00028050, 1, 0, "DB_Z_WRITE_BASE"},
+	{0x00028054, 1, 0, "DB_STENCIL_WRITE_BASE"},
+};
+
+static const struct radeon_register EG_names_VGT[] = {
+	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, //s
+	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, //s
+	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, //s
+	{0x00028408, 0, 0, "VGT_INDX_OFFSET"}, //s
+	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, //s
+	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, //s
+	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, //s
+	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, //s
+	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, //s
+	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, //s
+};
+
+static const struct radeon_register EG_names_DRAW[] = { 
+	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
+	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},    //same
+	{0x000287E8, 1, 0, "VGT_DMA_BASE"},       //same
+	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, //same
+};
+
+static const struct radeon_register EG_names_VGT_EVENT[] = {
+	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, //done
+};
+
+static const struct radeon_register EG_names_CB_FLUSH[] = {
+};
+
+static const struct radeon_register EG_names_DB_FLUSH[] = {
+};
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/gen_eg_states.py b/src/gallium/winsys/r600/drm/gen_eg_states.py
new file mode 100644
index 00000000000..b2e5b2203a4
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/gen_eg_states.py
@@ -0,0 +1,39 @@
+import os
+import re
+
+def main():
+    fileIN = open('eg_states.h', 'r')
+    line = fileIN.readline()
+    next_is_reg = False
+    count = 0
+
+    print "/* This file is autogenerated from eg_states.h - do not edit directly */"
+    print "/* autogenerating script is gen_eg_states.py */"
+    print ""
+    while line:
+        if line[0:2] == "};":
+            if next_is_reg == True:
+                print "#define " + name + "_SIZE\t\t", count
+                print "#define " + name + "_PM4 128\t\t"
+            next_is_reg = False
+            count = 0
+            print ""
+    
+        if line[0:6] == "static":
+            name = line.rstrip("\n")
+            cline = name.split()
+            name = cline[4].split('[')
+            name = name[0].replace("_names", "")
+            print "/* " + name + " */"
+            next_is_reg = True
+        elif next_is_reg == True:
+            reg = line.split();
+            reg = reg[3].replace("},", "")
+            reg = reg.replace("\"", "")
+            print "#define " + name + "__" + reg + "\t\t", count
+            count = count + 1
+
+        line = fileIN.readline()
+
+if __name__ == "__main__":
+    main()
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 3160beace7e..3570ee1485e 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -46,7 +46,10 @@ static int r700_state_pm4_config(struct radeon_state *state);
 static int r600_state_pm4_db_flush(struct radeon_state *state);
 static int r600_state_pm4_cb_flush(struct radeon_state *state);
 
+static int eg_state_pm4_vgt(struct radeon_state *state);
+
 #include "r600_states.h"
+#include "eg_states.h"
 
 
 #define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } }
@@ -55,6 +58,12 @@ static int r600_state_pm4_cb_flush(struct radeon_state *state);
 #define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
 #define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
 
+#define EG_SUB_NONE(param) { { 0, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } }
+#define EG_SUB_PS(param) { R600_SHADER_PS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_VS(param) { R600_SHADER_VS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_GS(param) { R600_SHADER_GS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+#define EG_SUB_FS(param) { R600_SHADER_FS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
+
 /* some of these are overriden at runtime for R700 */
 struct radeon_stype_info r600_stypes[] = {
 	{ R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), },
@@ -89,6 +98,39 @@ struct radeon_stype_info r600_stypes[] = {
 };
 #define STYPES_SIZE Elements(r600_stypes)
 
+struct radeon_stype_info eg_stypes[] = {
+	{ R600_STATE_CONFIG, 1, 0, r700_state_pm4_config, EG_SUB_NONE(CONFIG), },
+	{ R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB_CNTL) },
+	{ R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(RASTERIZER) },
+	{ R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(VIEWPORT) },
+	{ R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(SCISSOR) },
+	{ R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(BLEND), },
+	{ R600_STATE_DSA, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DSA), },
+	{ R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_SHADER), EG_SUB_VS(VS_SHADER) } },
+	{ R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_CBUF), EG_SUB_VS(VS_CBUF) } },
+	{ R600_STATE_RESOURCE, 176, 0x20, r600_state_pm4_resource, { EG_SUB_PS(PS_RESOURCE), EG_SUB_VS(VS_RESOURCE), EG_SUB_GS(GS_RESOURCE), EG_SUB_FS(FS_RESOURCE)} },
+	{ R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER), EG_SUB_VS(VS_SAMPLER), EG_SUB_GS(GS_SAMPLER) } },
+	{ R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } },
+	{ R600_STATE_CB0, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB0) },
+	{ R600_STATE_CB1, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB1) },
+	{ R600_STATE_CB2, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB2) },
+	{ R600_STATE_CB3, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB3) },
+	{ R600_STATE_CB4, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB4) },
+	{ R600_STATE_CB5, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB5) },
+	{ R600_STATE_CB6, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB6) },
+	{ R600_STATE_CB7, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB7) },
+	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, EG_SUB_NONE(VGT_EVENT) },
+	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, EG_SUB_NONE(VGT_EVENT) },
+	{ R600_STATE_DB, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DB) },
+	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(UCP) },
+	{ R600_STATE_VGT, 1, 0, eg_state_pm4_vgt, EG_SUB_NONE(VGT) },
+	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, EG_SUB_NONE(DRAW) },
+	{ R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, EG_SUB_NONE(CB_FLUSH) },
+	{ R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, EG_SUB_NONE(DB_FLUSH) },
+
+};
+#define EG_STYPES_SIZE Elements(eg_stypes)
+
 static const struct radeon_register *get_regs(struct radeon_state *state)
 {
 	return state->stype->reginfo[state->shader_index].regs;
@@ -162,6 +204,72 @@ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset,
 	return -EINVAL;
 }
 
+static int eg_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
+{
+	const struct radeon_register *regs = get_regs(state);
+	unsigned i;
+	int r;
+
+	if (!offset) {
+		fprintf(stderr, "%s invalid register for state %d %d\n",
+			__func__, state->stype->stype, id);
+		return -EINVAL;
+	}
+	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= EG_RESOURCE_OFFSET && offset < EG_RESOURCE_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nreg);
+		state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
+	return -EINVAL;
+}
+
+
 static int r600_state_pm4_generic(struct radeon_state *state)
 {
 	const struct radeon_register *regs = get_regs(state);
@@ -180,7 +288,10 @@ static int r600_state_pm4_generic(struct radeon_state *state)
 			nreg++;
 			loffset = coffset;
 		} else {
-			r = r600_state_pm4_bytecode(state, offset, start, nreg);
+			if (state->radeon->family >= CHIP_CEDAR)
+				r = eg_state_pm4_bytecode(state, offset, start, nreg);
+			else
+				r = r600_state_pm4_bytecode(state, offset, start, nreg);
 			if (r) {
 				fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
 				return r;
@@ -190,7 +301,11 @@ static int r600_state_pm4_generic(struct radeon_state *state)
 			start = i;
 		}
 	}
-	return r600_state_pm4_bytecode(state, offset, start, nreg);
+	if (state->radeon->family >= CHIP_CEDAR)
+		r = eg_state_pm4_bytecode(state, offset, start, nreg);
+	else
+		r = r600_state_pm4_bytecode(state, offset, start, nreg);
+	return r;
 }
 
 static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
@@ -314,6 +429,28 @@ static int r600_state_pm4_shader(struct radeon_state *state)
 	return r600_state_pm4_generic(state);
 }
 
+static int eg_state_pm4_vgt(struct radeon_state *state)
+{
+	int r;
+	r = eg_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, EG_VGT__VGT_MAX_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = eg_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, EG_VGT__VGT_MIN_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = eg_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, EG_VGT__VGT_INDX_OFFSET, 1);
+	if (r)
+		return r;
+	r = eg_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, EG_VGT__VGT_PRIMITIVE_TYPE, 1);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
+	state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_INDEX_TYPE];
+	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_NUM_INSTANCES];
+	return 0;
+}
+
 static int r600_state_pm4_vgt(struct radeon_state *state)
 {
 	int r;
@@ -362,6 +499,7 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 	}
 	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
 	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+
 	return 0;
 }
 
@@ -390,11 +528,15 @@ static int r600_state_pm4_db_flush(struct radeon_state *state)
 static int r600_state_pm4_resource(struct radeon_state *state)
 {
 	u32 flags, type, nbo, offset, soffset;
-	int r;
+	int r, nres;
 	const struct radeon_register *regs = get_regs(state);
 
 	soffset = state->id * state->stype->stride;
-	type = G_038018_TYPE(state->states[6]);
+	if (state->radeon->family >= CHIP_CEDAR)
+		type = G_038018_TYPE(state->states[7]);
+	else
+		type = G_038018_TYPE(state->states[6]);
+
 	switch (type) {
 	case 2:
 		flags = S_0085F0_TC_ACTION_ENA(1);
@@ -413,8 +555,15 @@ static int r600_state_pm4_resource(struct radeon_state *state)
 	}
 	r600_state_pm4_with_flush(state, flags);
 	offset = regs[0].offset + soffset;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
-	state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
+	if (state->radeon->family >= CHIP_CEDAR)
+		nres = 8;
+	else
+		nres = 7;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nres);
+	if (state->radeon->family >= CHIP_CEDAR)
+		state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
+	else
+		state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
 	state->pm4[state->cpm4++] = state->states[0];
 	state->pm4[state->cpm4++] = state->states[1];
 	state->pm4[state->cpm4++] = state->states[2];
@@ -422,6 +571,9 @@ static int r600_state_pm4_resource(struct radeon_state *state)
 	state->pm4[state->cpm4++] = state->states[4];
 	state->pm4[state->cpm4++] = state->states[5];
 	state->pm4[state->cpm4++] = state->states[6];
+	if (state->radeon->family >= CHIP_CEDAR)
+		state->pm4[state->cpm4++] = state->states[7];
+
 	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
 	r = radeon_state_reloc(state, state->cpm4, 0);
 	if (r)
@@ -469,31 +621,43 @@ static void r600_modify_type_array(struct radeon *radeon)
 	}
 }
 
-static void r600_build_types_array(struct radeon *radeon)
+static void build_types_array(struct radeon *radeon, struct radeon_stype_info *types, int size)
 {
 	int i, j;
 	int id = 0;
 
-	for (i = 0; i < STYPES_SIZE; i++) {
-		r600_stypes[i].base_id = id;
-		r600_stypes[i].npm4 = 128;
-		if (r600_stypes[i].reginfo[0].shader_type == 0) {
-			id += r600_stypes[i].num;
+	for (i = 0; i < size; i++) {
+		types[i].base_id = id;
+		types[i].npm4 = 128;
+		if (types[i].reginfo[0].shader_type == 0) {
+			id += types[i].num;
 		} else {
 			for (j = 0; j < R600_SHADER_MAX; j++) {
-				if (r600_stypes[i].reginfo[j].shader_type)
-					id += r600_stypes[i].num;
+				if (types[i].reginfo[j].shader_type)
+					id += types[i].num;
 			}
 		}
 	}
-	radeon->stype = r600_stypes;
-	radeon->nstype = STYPES_SIZE;
+	radeon->stype = types;
+	radeon->nstype = size;
+}
 
+static void r600_build_types_array(struct radeon *radeon)
+{
+	build_types_array(radeon, r600_stypes, STYPES_SIZE);
 	r600_modify_type_array(radeon);
 }
 
+static void eg_build_types_array(struct radeon *radeon)
+{
+	build_types_array(radeon, eg_stypes, EG_STYPES_SIZE);
+}
+
 int r600_init(struct radeon *radeon)
 {
-	r600_build_types_array(radeon);
+	if (radeon->family >= CHIP_CEDAR)
+		eg_build_types_array(radeon);
+	else
+		r600_build_types_array(radeon);
 	return 0;
 }
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index e8c2dc0651c..05f31571f42 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -43,6 +43,15 @@
 #define R600_BOOL_CONST_OFFSET                 0X0003E380
 #define R600_BOOL_CONST_END                    0X00040000
 
+/* evergreen values */
+#define EG_RESOURCE_OFFSET                 0x00030000
+#define EG_RESOURCE_END                    0x00030400
+#define EG_LOOP_CONST_OFFSET               0x0003A200
+#define EG_LOOP_CONST_END                  0x0003A26C
+#define EG_BOOL_CONST_OFFSET               0x0003A500
+#define EG_BOOL_CONST_END                  0x0003A506
+
+
 #define PKT3_NOP                               0x10
 #define PKT3_INDIRECT_BUFFER_END               0x17
 #define PKT3_SET_PREDICATION                   0x20
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index e2d813ebac7..64ccc7db877 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -79,6 +79,11 @@ struct radeon *radeon_new(int fd, unsigned device)
 	case CHIP_RV730:
 	case CHIP_RV710:
 	case CHIP_RV740:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
 		if (r600_init(radeon)) {
 			return radeon_decref(radeon);
 		}
@@ -110,11 +115,6 @@ struct radeon *radeon_new(int fd, unsigned device)
 	case CHIP_RV560:
 	case CHIP_RV570:
 	case CHIP_R580:
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
 	default:
 		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
 			__func__, radeon->device);
-- 
cgit v1.2.3


From fd266ec62ca772a8551d2d7922d718d9d84bdf07 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 17 Sep 2010 10:41:50 -0400
Subject: r600g: alternative command stream building from context

Winsys context build a list of register block a register block is
a set of consecutive register that will be emited together in the
same pm4 packet (the various r600_block* are there to provide basic
grouping that try to take advantage of states that are linked together)
Some consecutive register are emited each in a different block,
for instance the various cb[0-7]_base. At winsys context creation,
the list of block is created & an index into the list of block. So
to find into which block a register is in you simply use the register
offset and lookup the block index. Block are grouped together into
group which are the various pkt3 group of config, context, resource,

Pipe state build a list of register each state want to modify,
beside register value it also give a register mask so only subpart
of a register can be updated by a given pipe state (the oring is
in the winsys) There is no prebuild register list or define for
each pipe state. Once pipe state are built they are bound to
the winsys context.

Each of this functions will go through the list of register and
will find into which block each reg falls and will update the
value of the block with proper masking (vs/ps resource/constant
are specialized variant with somewhat limited capabilities).

Each block modified by r600_context_pipe_state_set* is marked as
dirty and we update a count of dwords needed to emit all dirty
state so far.

r600_context_pipe_state_set* should be call only when pipe context
change some of the state (thus when pipe bind state or set state)

Then to draw primitive you make a call to r600_context_draw
void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw)
It will check if there is enough dwords in current cs buffer and
if not will flush. Once there is enough room it will copy packet
from dirty block and then add the draw packet3 to initiate the draw.

The flush will send the current cs, reset the count of dwords to
0 and remark all states that are enabled as dirty and recompute
the number of dwords needed to send the current context.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/Makefile         |    1 +
 src/gallium/drivers/r600/r600.h           |  244 ++++
 src/gallium/drivers/r600/r600_resource.c  |   12 +-
 src/gallium/drivers/r600/r600_resource.h  |    2 +-
 src/gallium/drivers/r600/r600_screen.c    |    2 +-
 src/gallium/drivers/r600/r600_state2.c    | 2227 +++++++++++++++++++++++++++++
 src/gallium/drivers/r600/r600_texture.c   |    2 +-
 src/gallium/drivers/r600/r600d.h          | 2106 ++++++++++++++++++++++++++-
 src/gallium/targets/dri-r600/target.c     |   23 +
 src/gallium/winsys/r600/drm/Makefile      |    2 +
 src/gallium/winsys/r600/drm/r600.c        |  129 ++
 src/gallium/winsys/r600/drm/r600_priv.h   |   56 +
 src/gallium/winsys/r600/drm/r600_state2.c | 1055 ++++++++++++++
 src/gallium/winsys/r600/drm/r600d.h       |   77 +-
 14 files changed, 5913 insertions(+), 25 deletions(-)
 create mode 100644 src/gallium/drivers/r600/r600.h
 create mode 100644 src/gallium/drivers/r600/r600_state2.c
 create mode 100644 src/gallium/winsys/r600/drm/r600.c
 create mode 100644 src/gallium/winsys/r600/drm/r600_priv.h
 create mode 100644 src/gallium/winsys/r600/drm/r600_state2.c

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile
index a5249e09aa3..3cdb963f978 100644
--- a/src/gallium/drivers/r600/Makefile
+++ b/src/gallium/drivers/r600/Makefile
@@ -8,6 +8,7 @@ LIBRARY_INCLUDES = \
 
 C_SOURCES = \
 	r600_buffer.c \
+	r600_state2.c \
 	r600_context.c \
 	r600_shader.c \
 	r600_draw.c \
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
new file mode 100644
index 00000000000..bce2707e770
--- /dev/null
+++ b/src/gallium/drivers/r600/r600.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_H
+#define R600_H
+
+#include <stdint.h>
+#include <stdio.h>
+
+#define RADEON_CTX_MAX_PM4	(64 * 1024 / 4)
+
+#define R600_ERR(fmt, args...) \
+	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
+
+typedef uint64_t		u64;
+typedef uint32_t		u32;
+typedef uint16_t		u16;
+typedef uint8_t			u8;
+
+struct radeon;
+
+enum radeon_family {
+	CHIP_UNKNOWN,
+	CHIP_R100,
+	CHIP_RV100,
+	CHIP_RS100,
+	CHIP_RV200,
+	CHIP_RS200,
+	CHIP_R200,
+	CHIP_RV250,
+	CHIP_RS300,
+	CHIP_RV280,
+	CHIP_R300,
+	CHIP_R350,
+	CHIP_RV350,
+	CHIP_RV380,
+	CHIP_R420,
+	CHIP_R423,
+	CHIP_RV410,
+	CHIP_RS400,
+	CHIP_RS480,
+	CHIP_RS600,
+	CHIP_RS690,
+	CHIP_RS740,
+	CHIP_RV515,
+	CHIP_R520,
+	CHIP_RV530,
+	CHIP_RV560,
+	CHIP_RV570,
+	CHIP_R580,
+	CHIP_R600,
+	CHIP_RV610,
+	CHIP_RV630,
+	CHIP_RV670,
+	CHIP_RV620,
+	CHIP_RV635,
+	CHIP_RS780,
+	CHIP_RS880,
+	CHIP_RV770,
+	CHIP_RV730,
+	CHIP_RV710,
+	CHIP_RV740,
+	CHIP_CEDAR,
+	CHIP_REDWOOD,
+	CHIP_JUNIPER,
+	CHIP_CYPRESS,
+	CHIP_HEMLOCK,
+	CHIP_LAST,
+};
+
+enum radeon_family r600_get_family(struct radeon *rw);
+
+/*
+ * radeon object functions
+ */
+#if 0
+struct radeon_bo {
+	unsigned			refcount;
+	unsigned			handle;
+	unsigned			size;
+	unsigned			alignment;
+	unsigned			map_count;
+	void				*data;
+};
+struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
+			unsigned size, unsigned alignment, void *ptr);
+int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
+struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
+struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
+int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
+#endif
+/* lowlevel WS bo */
+struct radeon_ws_bo;
+struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+				  unsigned size, unsigned alignment, unsigned usage);
+struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+					 unsigned handle);
+void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
+void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
+void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
+			    struct radeon_ws_bo *src);
+int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *bo);
+
+/* R600/R700 STATES */
+#define R600_GROUP_MAX			16
+#define R600_BLOCK_MAX_BO		32
+#define R600_BLOCK_MAX_REG		128
+
+enum r600_group_id {
+	R600_GROUP_CONFIG = 0,
+	R600_GROUP_CONTEXT,
+	R600_GROUP_ALU_CONST,
+	R600_GROUP_RESOURCE,
+	R600_GROUP_SAMPLER,
+	R600_GROUP_CTL_CONST,
+	R600_GROUP_LOOP_CONST,
+	R600_GROUP_BOOL_CONST,
+	R600_NGROUPS
+};
+
+struct r600_pipe_reg {
+	unsigned			group_id;
+	u32				offset;
+	u32				mask;
+	u32				value;
+	struct radeon_ws_bo		*bo;
+};
+
+struct r600_pipe_state {
+	unsigned			id;
+	unsigned			nregs;
+	struct r600_pipe_reg		regs[R600_BLOCK_MAX_REG];
+};
+
+static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
+					unsigned group_id, u32 offset,
+					u32 value, u32 mask,
+					struct radeon_ws_bo *bo)
+{
+	state->regs[state->nregs].group_id = group_id;
+	state->regs[state->nregs].offset = offset;
+	state->regs[state->nregs].value = value;
+	state->regs[state->nregs].mask = mask;
+	state->regs[state->nregs].bo = bo;
+	state->nregs++;
+	assert(state->nregs < R600_BLOCK_MAX_REG);
+}
+
+#define R600_BLOCK_STATUS_ENABLED	(1 << 0)
+#define R600_BLOCK_STATUS_DIRTY		(1 << 1)
+
+struct r600_block_reloc {
+	struct radeon_ws_bo	*bo;
+	unsigned		nreloc;
+	unsigned		bo_pm4_index[R600_BLOCK_MAX_BO];
+};
+
+struct r600_group_block {
+	unsigned		status;
+	unsigned		start_offset;
+	unsigned		pm4_ndwords;
+	unsigned		nbo;
+	unsigned		nreg;
+	u32			pm4[R600_BLOCK_MAX_REG];
+	unsigned		pm4_bo_index[R600_BLOCK_MAX_REG];
+	struct r600_block_reloc	reloc[R600_BLOCK_MAX_BO];
+};
+
+struct r600_group {
+	unsigned		start_offset;
+	unsigned		end_offset;
+	unsigned		nblocks;
+	struct r600_group_block	*blocks;
+	unsigned		*offset_block_id;
+};
+
+#pragma pack(1)
+struct r600_reloc {
+	uint32_t	handle;
+	uint32_t	read_domain;
+	uint32_t	write_domain;
+	uint32_t	flags;
+};
+#pragma pack()
+
+struct r600_context {
+	struct radeon		*radeon;
+	unsigned		ngroups;
+	struct r600_group	groups[R600_GROUP_MAX];
+	unsigned		pm4_ndwords;
+	unsigned		pm4_cdwords;
+	unsigned		pm4_dirty_cdwords;
+	unsigned		ctx_pm4_ndwords;
+	unsigned		nreloc;
+	unsigned		creloc;
+	struct r600_reloc	*reloc;
+	struct radeon_ws_bo	**bo;
+	u32			*pm4;
+};
+
+struct r600_draw {
+	u32			vgt_num_indices;
+	u32			vgt_num_instances;
+	u32			vgt_index_type;
+	u32			vgt_draw_initiator;
+	u32			indices_bo_offset;
+	struct radeon_ws_bo	*indices;
+};
+
+int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
+void r600_context_fini(struct r600_context *ctx);
+void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+void r600_context_flush(struct r600_context *ctx);
+void r600_context_dump_bof(struct r600_context *ctx, const char *file);
+void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
+
+#endif
diff --git a/src/gallium/drivers/r600/r600_resource.c b/src/gallium/drivers/r600/r600_resource.c
index 8dc411ef409..05707740da5 100644
--- a/src/gallium/drivers/r600/r600_resource.c
+++ b/src/gallium/drivers/r600/r600_resource.c
@@ -57,11 +57,11 @@ void r600_init_context_resource_functions(struct r600_context *r600)
 	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
 }
 
-void r600_init_screen_resource_functions(struct r600_screen *r600screen)
+void r600_init_screen_resource_functions(struct pipe_screen *screen)
 {
-	r600screen->screen.resource_create = r600_resource_create;
-	r600screen->screen.resource_from_handle = r600_resource_from_handle;
-	r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
-	r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
-	r600screen->screen.user_buffer_create = r600_user_buffer_create;
+	screen->resource_create = r600_resource_create;
+	screen->resource_from_handle = r600_resource_from_handle;
+	screen->resource_get_handle = u_resource_get_handle_vtbl;
+	screen->resource_destroy = u_resource_destroy_vtbl;
+	screen->user_buffer_create = r600_user_buffer_create;
 }
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 9608a5a6234..6ddb1ad32a7 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -63,7 +63,7 @@ struct r600_resource_texture {
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
-void r600_init_screen_resource_functions(struct r600_screen *r600screen);
+void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
 /* r600_buffer */
 u32 r600_domain_from_usage(unsigned usage);
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index 9860221219e..1711fabfc7a 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -287,6 +287,6 @@ struct pipe_screen *r600_screen_create(struct radeon *rw)
 	rscreen->screen.is_format_supported = r600_is_format_supported;
 	rscreen->screen.context_create = r600_create_context;
 	r600_init_screen_texture_functions(&rscreen->screen);
-	r600_init_screen_resource_functions(rscreen);
+	r600_init_screen_resource_functions(&rscreen->screen);
 	return &rscreen->screen;
 }
diff --git a/src/gallium/drivers/r600/r600_state2.c b/src/gallium/drivers/r600/r600_state2.c
new file mode 100644
index 00000000000..63cc19708b1
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_state2.c
@@ -0,0 +1,2227 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* TODO:
+ *	- fix mask for depth control & cull for query
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <pipebuffer/pb_buffer.h>
+#include "state_tracker/drm_driver.h"
+#include "r600.h"
+#include "r600d.h"
+#include "r700_sq.h"
+struct radeon_state {
+	unsigned dummy;
+};
+#include "r600_resource.h"
+#include "r600_shader.h"
+
+
+uint32_t r600_translate_texformat(enum pipe_format format,
+				  const unsigned char *swizzle_view, 
+				  uint32_t *word4_p, uint32_t *yuv_format_p);
+
+#include "r600_state_inlines.h"
+
+enum chip_class {
+	R600,
+	R700,
+	EVERGREEN,
+};
+
+enum r600_pipe_state_id {
+	R600_PIPE_STATE_BLEND = 0,
+	R600_PIPE_STATE_BLEND_COLOR,
+	R600_PIPE_STATE_CONFIG,
+	R600_PIPE_STATE_CLIP,
+	R600_PIPE_STATE_SCISSOR,
+	R600_PIPE_STATE_VIEWPORT,
+	R600_PIPE_STATE_RASTERIZER,
+	R600_PIPE_STATE_VGT,
+	R600_PIPE_STATE_FRAMEBUFFER,
+	R600_PIPE_STATE_DSA,
+	R600_PIPE_STATE_STENCIL_REF,
+	R600_PIPE_STATE_PS_SHADER,
+	R600_PIPE_STATE_VS_SHADER,
+	R600_PIPE_STATE_CONSTANT,
+	R600_PIPE_STATE_SAMPLER,
+	R600_PIPE_STATE_RESOURCE,
+	R600_PIPE_NSTATES
+};
+
+struct r600_screen {
+	struct pipe_screen		screen;
+	struct radeon			*radeon;
+	unsigned			chip_class;
+};
+
+struct r600_pipe_sampler_view {
+	struct pipe_sampler_view	base;
+	struct r600_pipe_state		state;
+};
+
+struct r600_pipe_rasterizer {
+	struct r600_pipe_state		rstate;
+	bool				flatshade;
+	unsigned			sprite_coord_enable;
+};
+
+struct r600_pipe_blend {
+	struct r600_pipe_state		rstate;
+	unsigned			cb_target_mask;
+};
+
+struct r600_pipe_shader {
+	struct r600_shader		shader;
+	struct r600_pipe_state		rstate;
+	struct radeon_ws_bo		*bo;
+};
+
+struct r600_vertex_element
+{
+	unsigned			count;
+	unsigned			refcount;
+	struct pipe_vertex_element	elements[32];
+};
+
+struct r600_pipe_context {
+	struct pipe_context		context;
+	struct r600_screen		*screen;
+	struct radeon			*radeon;
+	struct blitter_context		*blitter;
+	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
+	struct r600_context		ctx;
+	struct r600_vertex_element	*vertex_elements;
+	struct pipe_framebuffer_state	framebuffer;
+	struct pipe_index_buffer	index_buffer;
+	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
+	unsigned			nvertex_buffer;
+	unsigned			cb_target_mask;
+	/* for saving when using blitter */
+	struct pipe_stencil_ref		stencil_ref;
+	struct pipe_viewport_state	viewport;
+	struct pipe_clip_state		clip;
+	unsigned			vs_nconst;
+	unsigned			ps_nconst;
+	struct r600_pipe_state		vs_const[256];
+	struct r600_pipe_state		ps_const[256];
+	struct r600_pipe_state		vs_resource[160];
+	struct r600_pipe_state		ps_resource[160];
+	struct r600_pipe_state		config;
+	struct r600_pipe_shader 	*ps_shader;
+	struct r600_pipe_shader 	*vs_shader;
+	/* shader information */
+	bool				ps_rebuild;
+	bool				vs_rebuild;
+	unsigned			sprite_coord_enable;
+	bool				flatshade;
+};
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+
+/* r600_shader.c */
+static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned spi_vs_out_id[10];
+	unsigned i, tmp;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	/* so far never got proper semantic id from tgsi */
+	for (i = 0; i < 10; i++) {
+		spi_vs_out_id[i] = 0;
+	}
+	for (i = 0; i < 32; i++) {
+		tmp = i << ((i & 3) * 8);
+		spi_vs_out_id[i / 4] |= tmp;
+	}
+	for (i = 0; i < 10; i++) {
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+					R_028614_SPI_VS_OUT_ID_0 + i * 4,
+					spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+	}
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_0286C4_SPI_VS_OUT_CONFIG,
+			S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_028868_SQ_PGM_RESOURCES_VS,
+			S_028868_NUM_GPRS(rshader->bc.ngpr) |
+			S_028868_STACK_SIZE(rshader->bc.nstack),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_0288A4_SQ_PGM_RESOURCES_FS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_0288D0_SQ_PGM_CF_OFFSET_VS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_0288DC_SQ_PGM_CF_OFFSET_FS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_028858_SQ_PGM_START_VS,
+			0x00000000, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+			R_028894_SQ_PGM_START_FS,
+			0x00000000, 0xFFFFFFFF, shader->bo);
+	rctx->vs_rebuild = false;
+}
+
+static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
+	boolean have_pos = FALSE;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	for (i = 0; i < rshader->ninput; i++) {
+		tmp = S_028644_SEMANTIC(i);
+		tmp |= S_028644_SEL_CENTROID(1);
+		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+			have_pos = TRUE;
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
+		if (rctx->sprite_coord_enable & (1 << i)) {
+			tmp |= S_028644_PT_SPRITE_TEX(1);
+		}
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			exports_ps |= (1 << (num_cout+1));
+			num_cout++;
+		}
+	}
+	if (!exports_ps) {
+		/* always at least export 1 component per pixel */
+		exports_ps = 2;
+	}
+
+	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
+				S_0286CC_PERSP_GRADIENT_ENA(1);
+	spi_input_z = 0;
+	if (have_pos) {
+		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
+					S_0286CC_BARYC_SAMPLE_CNTL(1);
+		spi_input_z |= 1;
+	}
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028840_SQ_PGM_START_PS,
+				0x00000000, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028850_SQ_PGM_RESOURCES_PS,
+				S_028868_NUM_GPRS(rshader->bc.ngpr) |
+				S_028868_STACK_SIZE(rshader->bc.nstack),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028854_SQ_PGM_EXPORTS_PS,
+				exports_ps, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_0288CC_SQ_PGM_CF_OFFSET_PS,
+				0x00000000, 0xFFFFFFFF, NULL);
+	rctx->ps_rebuild = false;
+}
+
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_shader *rshader = &shader->shader;
+	void *ptr;
+
+	/* copy new shader */
+	if (shader->bo == NULL) {
+		shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
+		if (shader->bo == NULL) {
+			return -ENOMEM;
+		}
+		ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
+		memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
+		radeon_ws_bo_unmap(rctx->radeon, shader->bo);
+	}
+	/* build state */
+	rshader->flat_shade = rctx->flatshade;
+	switch (rshader->processor_type) {
+	case TGSI_PROCESSOR_VERTEX:
+		r600_pipe_shader_vs(ctx, shader);
+		break;
+	case TGSI_PROCESSOR_FRAGMENT:
+		r600_pipe_shader_ps(ctx, shader);
+		break;
+	default:
+		return -EINVAL;
+	}
+	r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+	return 0;
+}
+
+static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_shader *shader = &rshader->shader;
+	const struct util_format_description *desc;
+	enum pipe_format resource_format[160];
+	unsigned i, nresources = 0;
+	struct r600_bc *bc = &shader->bc;
+	struct r600_bc_cf *cf;
+	struct r600_bc_vtx *vtx;
+
+	if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
+		return 0;
+	for (i = 0; i < rctx->vertex_elements->count; i++) {
+		resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
+	}
+	radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
+	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
+		switch (cf->inst) {
+		case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+		case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+			LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+				desc = util_format_description(resource_format[vtx->buffer_id]);
+				if (desc == NULL) {
+					R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
+					return -EINVAL;
+				}
+				vtx->dst_sel_x = desc->swizzle[0];
+				vtx->dst_sel_y = desc->swizzle[1];
+				vtx->dst_sel_z = desc->swizzle[2];
+				vtx->dst_sel_w = desc->swizzle[3];
+			}
+			break;
+		default:
+			break;
+		}
+	}
+	return r600_bc_build(&shader->bc);
+}
+
+static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	int r;
+
+	if (shader == NULL)
+		return -EINVAL;
+	if (shader->bo) {
+		switch (shader->shader.processor_type) {
+		case TGSI_PROCESSOR_VERTEX:
+			if (!rctx->vs_rebuild)
+				return 0;
+			break;
+		case TGSI_PROCESSOR_FRAGMENT:
+			if (!rctx->ps_rebuild)
+				return 0;
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+	/* there should be enough input */
+	if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
+		R600_ERR("%d resources provided, expecting %d\n",
+			rctx->vertex_elements->count, shader->shader.bc.nresource);
+		return -EINVAL;
+	}
+	r = r600_shader_update(ctx, shader);
+	if (r)
+		return r;
+	return r600_pipe_shader(ctx, shader);
+}
+
+int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
+static int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	int r;
+
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
+	shader->shader.family = r600_get_family(rctx->radeon);
+	r = r600_shader_from_tgsi(tokens, &shader->shader);
+	if (r) {
+		R600_ERR("translation from TGSI failed !\n");
+		return r;
+	}
+	r = r600_bc_build(&shader->shader.bc);
+	if (r) {
+		R600_ERR("building bytecode failed !\n");
+		return r;
+	}
+//fprintf(stderr, "______________________________________________________________\n");
+	return 0;
+}
+/* r600_shader.c END */
+
+static const char* r600_get_vendor(struct pipe_screen* pscreen)
+{
+	return "X.Org";
+}
+
+static const char* r600_get_name(struct pipe_screen* pscreen)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	enum radeon_family family = r600_get_family(rscreen->radeon);
+
+	if (family >= CHIP_R600 && family < CHIP_RV770)
+		return "R600 (HD2XXX,HD3XXX)";
+	else
+		return "R700 (HD4XXX)";
+}
+
+static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+	switch (param) {
+	/* Supported features (boolean caps). */
+	case PIPE_CAP_NPOT_TEXTURES:
+	case PIPE_CAP_TWO_SIDED_STENCIL:
+	case PIPE_CAP_GLSL:
+	case PIPE_CAP_DUAL_SOURCE_BLEND:
+	case PIPE_CAP_ANISOTROPIC_FILTER:
+	case PIPE_CAP_POINT_SPRITE:
+	case PIPE_CAP_OCCLUSION_QUERY:
+	case PIPE_CAP_TEXTURE_SHADOW_MAP:
+	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+	case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
+	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
+	case PIPE_CAP_SM3:
+	case PIPE_CAP_TEXTURE_SWIZZLE:
+	case PIPE_CAP_INDEP_BLEND_ENABLE:
+	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+	case PIPE_CAP_DEPTH_CLAMP:
+		return 1;
+
+	/* Unsupported features (boolean caps). */
+	case PIPE_CAP_TIMER_QUERY:
+	case PIPE_CAP_STREAM_OUTPUT:
+	case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
+		return 0;
+
+	/* Texturing. */
+	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+		return 14;
+	case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+		/* FIXME allow this once infrastructure is there */
+		return 0;
+	case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+	case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+		return 16;
+
+	/* Render targets. */
+	case PIPE_CAP_MAX_RENDER_TARGETS:
+		/* FIXME some r6xx are buggy and can only do 4 */
+		return 8;
+
+	/* Fragment coordinate conventions. */
+	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+		return 1;
+	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+		return 0;
+
+	default:
+		R600_ERR("r600: unknown param %d\n", param);
+		return 0;
+	}
+}
+
+static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+	switch (param) {
+	case PIPE_CAP_MAX_LINE_WIDTH:
+	case PIPE_CAP_MAX_LINE_WIDTH_AA:
+	case PIPE_CAP_MAX_POINT_WIDTH:
+	case PIPE_CAP_MAX_POINT_WIDTH_AA:
+		return 8192.0f;
+	case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+		return 16.0f;
+	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+		return 16.0f;
+	default:
+		R600_ERR("r600: unsupported paramf %d\n", param);
+		return 0.0f;
+	}
+}
+
+static boolean r600_is_format_supported(struct pipe_screen* screen,
+					enum pipe_format format,
+					enum pipe_texture_target target,
+					unsigned sample_count,
+					unsigned usage,
+					unsigned geom_flags)
+{
+	unsigned retval = 0;
+	if (target >= PIPE_MAX_TEXTURE_TYPES) {
+		R600_ERR("r600: unsupported texture type %d\n", target);
+		return FALSE;
+	}
+
+	/* Multisample */
+	if (sample_count > 1)
+		return FALSE;
+
+	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+	    r600_is_sampler_format_supported(format)) {
+		retval |= PIPE_BIND_SAMPLER_VIEW;
+	}
+
+	if ((usage & (PIPE_BIND_RENDER_TARGET |
+                  PIPE_BIND_DISPLAY_TARGET |
+                  PIPE_BIND_SCANOUT |
+                  PIPE_BIND_SHARED)) &&
+	    r600_is_colorbuffer_format_supported(format)) {
+		retval |= usage &
+			(PIPE_BIND_RENDER_TARGET |
+			 PIPE_BIND_DISPLAY_TARGET |
+			 PIPE_BIND_SCANOUT |
+			 PIPE_BIND_SHARED);
+	}
+
+	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+	    r600_is_zs_format_supported(format)) {
+		retval |= PIPE_BIND_DEPTH_STENCIL;
+	}
+
+	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+	    r600_is_vertex_format_supported(format))
+		retval |= PIPE_BIND_VERTEX_BUFFER;
+
+	if (usage & PIPE_BIND_TRANSFER_READ)
+		retval |= PIPE_BIND_TRANSFER_READ;
+	if (usage & PIPE_BIND_TRANSFER_WRITE)
+		retval |= PIPE_BIND_TRANSFER_WRITE;
+
+	return retval == usage;
+}
+
+static void r600_destroy_screen(struct pipe_screen* pscreen)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+
+	if (rscreen == NULL)
+		return;
+	FREE(rscreen);
+}
+
+struct r600_drawl {
+	struct pipe_context	*ctx;
+	unsigned		mode;
+	unsigned		start;
+	unsigned		count;
+	unsigned		index_size;
+	struct pipe_resource	*index_buffer;
+};
+
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+static void r600_draw_common(struct r600_drawl *draw)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
+	struct r600_pipe_state *rstate;
+	struct r600_resource *rbuffer;
+	unsigned i, j, offset, format, prim;
+	u32 vgt_dma_index_type, vgt_draw_initiator, mask;
+	struct pipe_vertex_buffer *vertex_buffer;
+	struct r600_draw rdraw;
+	struct r600_pipe_state vgt;
+
+	switch (draw->index_size) {
+	case 2:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 0;
+		break;
+	case 4:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 1;
+		break;
+	case 0:
+		vgt_draw_initiator = 2;
+		vgt_dma_index_type = 0;
+		break;
+	default:
+		R600_ERR("unsupported index size %d\n", draw->index_size);
+		return;
+	}
+	if (r600_conv_pipe_prim(draw->mode, &prim))
+		return;
+
+	/* rebuild vertex shader if input format changed */
+	if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
+		return;
+	if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
+		return;
+
+	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+		rstate = &rctx->vs_resource[i];
+		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
+		vertex_buffer = &rctx->vertex_buffer[j];
+		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
+		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
+		rstate->id = R600_PIPE_STATE_RESOURCE;
+		rstate->nregs = 0;
+
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE,
+					R_038008_RESOURCE0_WORD2,
+					S_038008_STRIDE(vertex_buffer->stride) |
+					S_038008_DATA_FORMAT(format),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
+		r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
+	}
+
+	mask = 0;
+	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+		mask |= (0xF << (i * 4));
+	}
+
+	vgt.id = R600_PIPE_STATE_VGT;
+	vgt.nregs = 0;
+	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw->start, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+	r600_context_pipe_state_set(&rctx->ctx, &vgt);
+
+	rdraw.vgt_num_indices = draw->count;
+	rdraw.vgt_num_instances = 1;
+	rdraw.vgt_index_type = vgt_dma_index_type;
+	rdraw.vgt_draw_initiator = vgt_draw_initiator;
+	rdraw.indices = NULL;
+	if (draw->index_buffer) {
+		rbuffer = (struct r600_resource*)draw->index_buffer;
+		rdraw.indices = rbuffer->bo;
+	}
+	r600_context_draw(&rctx->ctx, &rdraw);
+}
+
+static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_drawl draw;
+
+	assert(info->index_bias == 0);
+
+	draw.ctx = ctx;
+	draw.mode = info->mode;
+	draw.start = info->start;
+	draw.count = info->count;
+	if (info->indexed && rctx->index_buffer.buffer) {
+		draw.index_size = rctx->index_buffer.index_size;
+		draw.index_buffer = rctx->index_buffer.buffer;
+		assert(rctx->index_buffer.offset %
+				rctx->index_buffer.index_size == 0);
+		draw.start += rctx->index_buffer.offset /
+			rctx->index_buffer.index_size;
+	} else {
+		draw.index_size = 0;
+		draw.index_buffer = NULL;
+	}
+	r600_draw_common(&draw);
+}
+
+static void r600_flush2(struct pipe_context *ctx, unsigned flags,
+			struct pipe_fence_handle **fence)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	static int dc = 0;
+	char dname[256];
+
+	if (!rctx->ctx.pm4_cdwords)
+		return;
+
+#if 0
+	sprintf(dname, "gallium-%08d.bof", dc);
+	if (dc < 2) {
+		r600_context_dump_bof(&rctx->ctx, dname);
+		R600_ERR("dumped %s\n", dname);
+	}
+	dc++;
+#endif
+	r600_context_flush(&rctx->ctx);
+}
+
+static void r600_destroy_context(struct pipe_context *context)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
+
+	r600_context_fini(&rctx->ctx);
+	for (int i = 0; i < R600_PIPE_NSTATES; i++) {
+		free(rctx->states[i]);
+	}
+	FREE(rctx);
+}
+
+static void r600_blitter_save_states(struct pipe_context *ctx)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
+	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
+	if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
+		util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
+	}
+	util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
+	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
+	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
+	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
+	if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
+		util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
+	}
+	if (rctx->states[R600_PIPE_STATE_CLIP]) {
+		util_blitter_save_clip(rctx->blitter, &rctx->clip);
+	}
+	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
+
+	rctx->vertex_elements = NULL;
+
+	/* TODO queries */
+}
+
+static void r600_clear(struct pipe_context *ctx, unsigned buffers,
+			const float *rgba, double depth, unsigned stencil)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+	r600_blitter_save_states(ctx);
+	util_blitter_clear(rctx->blitter, fb->width, fb->height,
+				fb->nr_cbufs, buffers, rgba, depth,
+				stencil);
+}
+
+static void r600_clear_render_target(struct pipe_context *ctx,
+				     struct pipe_surface *dst,
+				     const float *rgba,
+				     unsigned dstx, unsigned dsty,
+				     unsigned width, unsigned height)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+	util_blitter_save_framebuffer(rctx->blitter, fb);
+	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
+					 dstx, dsty, width, height);
+}
+
+static void r600_clear_depth_stencil(struct pipe_context *ctx,
+				     struct pipe_surface *dst,
+				     unsigned clear_flags,
+				     double depth,
+				     unsigned stencil,
+				     unsigned dstx, unsigned dsty,
+				     unsigned width, unsigned height)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+	util_blitter_save_framebuffer(rctx->blitter, fb);
+	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
+					 dstx, dsty, width, height);
+}
+
+
+static void r600_resource_copy_region(struct pipe_context *ctx,
+				      struct pipe_resource *dst,
+				      struct pipe_subresource subdst,
+				      unsigned dstx, unsigned dsty, unsigned dstz,
+				      struct pipe_resource *src,
+				      struct pipe_subresource subsrc,
+				      unsigned srcx, unsigned srcy, unsigned srcz,
+				      unsigned width, unsigned height)
+{
+	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+				  src, subsrc, srcx, srcy, srcz, width, height);
+}
+
+static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
+{
+	rctx->context.clear = r600_clear;
+	rctx->context.clear_render_target = r600_clear_render_target;
+	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
+	rctx->context.resource_copy_region = r600_resource_copy_region;
+}
+
+static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
+{
+	r600->context.get_transfer = u_get_transfer_vtbl;
+	r600->context.transfer_map = u_transfer_map_vtbl;
+	r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+	r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+	r600->context.transfer_destroy = u_transfer_destroy_vtbl;
+	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
+	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
+}
+
+static void r600_set_blend_color(struct pipe_context *ctx,
+					const struct pipe_blend_color *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rstate->id = R600_PIPE_STATE_BLEND_COLOR;
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
+	free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
+	rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *r600_create_blend_state(struct pipe_context *ctx,
+					const struct pipe_blend_state *state)
+{
+	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
+	struct r600_pipe_state *rstate;
+	u32 color_control, target_mask;
+
+	if (blend == NULL) {
+		return NULL;
+	}
+	rstate = &blend->rstate;
+
+	rstate->id = R600_PIPE_STATE_BLEND;
+
+	target_mask = 0;
+	color_control = S_028808_PER_MRT_BLEND(1);
+	if (state->logicop_enable) {
+		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
+	} else {
+		color_control |= (0xcc << 16);
+	}
+	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+	if (state->independent_blend_enable) {
+		for (int i = 0; i < 8; i++) {
+			if (state->rt[i].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (state->rt[i].colormask << (4 * i));
+		}
+	} else {
+		for (int i = 0; i < 8; i++) {
+			if (state->rt[0].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (state->rt[0].colormask << (4 * i));
+		}
+	}
+	blend->cb_target_mask = target_mask;
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
+				color_control, 0xFFFFFFFF, NULL);
+
+	for (int i = 0; i < 8; i++) {
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+		uint32_t bc = 0;
+
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
+			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+		}
+
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
+		if (i == 0) {
+			r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
+		}
+	}
+	return rstate;
+}
+
+static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
+	struct r600_pipe_state *rstate;
+
+	if (state == NULL)
+		return;
+	rstate = &blend->rstate;
+	rctx->states[rstate->id] = rstate;
+	rctx->cb_target_mask = blend->cb_target_mask;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *r600_create_dsa_state(struct pipe_context *ctx,
+				   const struct pipe_depth_stencil_alpha_state *state)
+{
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+
+	if (rstate == NULL) {
+		return NULL;
+	}
+
+	rstate->id = R600_PIPE_STATE_DSA;
+	/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
+	/* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
+	 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
+	 * be set if shader use texkill instruction
+	 */
+	db_shader_control = 0x210;
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+
+	/* stencil */
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+		}
+	}
+
+	/* alpha */
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+		alpha_ref = fui(state->alpha.ref_value);
+	}
+
+	/* misc */
+	db_render_control = 0;
+	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+	/* TODO db_render_override depends on query */
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028430_DB_STENCILREFMASK, stencil_ref_mask,
+				0xFFFFFFFF & C_028430_STENCILREF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
+				0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
+
+	return rstate;
+}
+
+static void *r600_create_rs_state(struct pipe_context *ctx,
+					const struct pipe_rasterizer_state *state)
+{
+	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
+	struct r600_pipe_state *rstate;
+	float offset_units = 0, offset_scale = 0;
+	unsigned offset_db_fmt_cntl = 0;
+	unsigned tmp;
+	unsigned prov_vtx = 1;
+
+	if (rs == NULL) {
+		return NULL;
+	}
+
+	rstate = &rs->rstate;
+	rs->flatshade = state->flatshade;
+	rs->sprite_coord_enable = state->sprite_coord_enable;
+
+	rstate->id = R600_PIPE_STATE_RASTERIZER;
+	if (state->flatshade_first)
+		prov_vtx = 0;
+	tmp = 0x00000001;
+	if (state->sprite_coord_enable) {
+		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+			S_0286D4_PNT_SPRITE_OVRD_X(2) |
+			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+			S_0286D4_PNT_SPRITE_OVRD_W(1);
+		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
+		}
+	}
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
+		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+		S_028814_FACE(!state->front_ccw) |
+		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
+			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	/* point size 12.4 fixed point */
+	tmp = (unsigned)(state->point_size * 8.0);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+	return rstate;
+}
+
+static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	if (state == NULL)
+		return;
+
+	if (rctx->flatshade != rs->flatshade) {
+		rctx->ps_rebuild = true;
+	}
+	if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
+		rctx->ps_rebuild = true;
+	}
+	rctx->flatshade = rs->flatshade;
+	rctx->sprite_coord_enable = rs->sprite_coord_enable;
+
+	rctx->states[rs->rstate.id] = &rs->rstate;
+	r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
+}
+
+static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+
+	if (rctx->states[rs->rstate.id] == &rs->rstate) {
+		rctx->states[rs->rstate.id] = NULL;
+	}
+	free(rs);
+}
+
+static void *r600_create_sampler_state(struct pipe_context *ctx,
+					const struct pipe_sampler_state *state)
+{
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	union util_color uc;
+
+	if (rstate == NULL) {
+		return NULL;
+	}
+
+	rstate->id = R600_PIPE_STATE_SAMPLER;
+	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
+	/* FIXME LOD it depends on texture base level ... */
+	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
+			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
+	if (uc.ui) {
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
+	}
+	return rstate;
+}
+
+static void *r600_create_vertex_elements(struct pipe_context *ctx,
+				unsigned count,
+				const struct pipe_vertex_element *elements)
+{
+	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+	assert(count < 32);
+	v->count = count;
+	v->refcount = 1;
+	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+	return v;
+}
+
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+				      struct pipe_sampler_view *state)
+{
+	struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+	pipe_resource_reference(&state->texture, NULL);
+	FREE(resource);
+}
+
+static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
+							struct pipe_resource *texture,
+							const struct pipe_sampler_view *state)
+{
+	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
+	struct r600_pipe_state *rstate;
+	const struct util_format_description *desc;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
+	unsigned format;
+	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
+	struct radeon_ws_bo *bo[2];
+
+	if (resource == NULL)
+		return NULL;
+	rstate = &resource->state;
+
+	/* initialize base object */
+	resource->base = *state;
+	resource->base.texture = NULL;
+	pipe_reference(NULL, &texture->reference);
+	resource->base.texture = texture;
+	resource->base.reference.count = 1;
+	resource->base.context = ctx;
+
+	swizzle[0] = state->swizzle_r;
+	swizzle[1] = state->swizzle_g;
+	swizzle[2] = state->swizzle_b;
+	swizzle[3] = state->swizzle_a;
+	format = r600_translate_texformat(texture->format,
+					  swizzle,
+					  &word4, &yuv_format);
+	if (format == ~0) {
+		format = 0;
+	}
+	desc = util_format_description(texture->format);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", texture->format);
+	}
+	tmp = (struct r600_resource_texture*)texture;
+	rbuffer = &tmp->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	/* FIXME depth texture decompression */
+	if (tmp->depth) {
+#if 0
+		r = r600_texture_from_depth(ctx, tmp, view->first_level);
+		if (r) {
+			return;
+		}
+		bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+		bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+#endif
+	}
+	pitch = (tmp->pitch[0] / tmp->bpt);
+	pitch = (pitch + 0x7) & ~0x7;
+
+	/* FIXME properly handle first level != 0 */
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,
+				S_038000_DIM(r600_tex_dim(texture->target)) |
+				S_038000_TILE_MODE(array_mode) |
+				S_038000_TILE_TYPE(tile_type) |
+				S_038000_PITCH((pitch / 8) - 1) |
+				S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1,
+				S_038004_TEX_HEIGHT(texture->height0 - 1) |
+				S_038004_TEX_DEPTH(texture->depth0 - 1) |
+				S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038008_RESOURCE0_WORD2,
+				tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3,
+				tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4,
+				word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
+				S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
+				S_038010_REQUEST_SIZE(1) |
+				S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5,
+				S_038014_LAST_LEVEL(state->last_level) |
+				S_038014_BASE_ARRAY(0) |
+				S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6,
+				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+
+	return &resource->base;
+}
+
+static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
+{
+	/* TODO */
+	assert(1);
+}
+
+static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
+
+	for (int i = 0; i < count; i++) {
+		if (resource[i]) {
+			r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
+		}
+	}
+}
+
+static void r600_bind_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+	if (state == NULL)
+		return;
+	rctx->states[rstate->id] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+	for (int i = 0; i < count; i++) {
+		r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
+	}
+}
+
+static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+	/* TODO implement */
+	for (int i = 0; i < count; i++) {
+		r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
+	}
+}
+
+static void r600_delete_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+	if (rctx->states[rstate->id] == rstate) {
+		rctx->states[rstate->id] = NULL;
+	}
+	for (int i = 0; i < rstate->nregs; i++) {
+		radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+	}
+	free(rstate);
+}
+
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	if (v == NULL)
+		return;
+	if (--v->refcount)
+		return;
+	free(v);
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+				const struct pipe_clip_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rctx->clip = *state;
+	rstate->id = R600_PIPE_STATE_CLIP;
+	for (int i = 0; i < state->nr; i++) {
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+					R_028E20_PA_CL_UCP0_X + i * 4,
+					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+					R_028E24_PA_CL_UCP0_Y + i * 4,
+					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+					R_028E28_PA_CL_UCP0_Z + i * 4,
+					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+					R_028E2C_PA_CL_UCP0_W + i * 4,
+					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
+	}
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
+			S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
+			S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
+			S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_CLIP]);
+	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	r600_delete_vertex_element(ctx, rctx->vertex_elements);
+	rctx->vertex_elements = v;
+	if (v) {
+		v->refcount++;
+		rctx->vs_rebuild = true;
+	}
+}
+
+static void r600_set_polygon_stipple(struct pipe_context *ctx,
+					 const struct pipe_poly_stipple *state)
+{
+}
+
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void r600_set_scissor_state(struct pipe_context *ctx,
+					const struct pipe_scissor_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tl, br;
+
+	if (rstate == NULL)
+		return;
+
+	rstate->id = R600_PIPE_STATE_SCISSOR;
+	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028210_PA_SC_CLIPRECT_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028214_PA_SC_CLIPRECT_0_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028218_PA_SC_CLIPRECT_1_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_02821C_PA_SC_CLIPRECT_1_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028220_PA_SC_CLIPRECT_2_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028224_PA_SC_CLIPRECT_2_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028228_PA_SC_CLIPRECT_3_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_02822C_PA_SC_CLIPRECT_3_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
+				0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
+	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_stencil_ref(struct pipe_context *ctx,
+				const struct pipe_stencil_ref *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tmp;
+
+	if (rstate == NULL)
+		return;
+
+	rctx->stencil_ref = *state;
+	rstate->id = R600_PIPE_STATE_STENCIL_REF;
+	tmp = S_028430_STENCILREF(state->ref_value[0]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028430_DB_STENCILREFMASK, tmp,
+				~C_028430_STENCILREF, NULL);
+	tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028434_DB_STENCILREFMASK_BF, tmp,
+				~C_028434_STENCILREF_BF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+	rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_viewport_state(struct pipe_context *ctx,
+					const struct pipe_viewport_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rctx->viewport = *state;
+	rstate->id = R600_PIPE_STATE_VIEWPORT;
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
+	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state, int cb)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+	struct radeon_ws_bo *bo[3];
+
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	bo[2] = rbuffer->bo;
+
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_SOURCE_FORMAT(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028040_CB_COLOR0_BASE + cb * 4,
+				state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_0280A0_CB_COLOR0_INFO + cb * 4,
+				color_info, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028060_CB_COLOR0_SIZE + cb * 4,
+				S_028060_PITCH_TILE_MAX(pitch) |
+				S_028060_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028080_CB_COLOR0_VIEW + cb * 4,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_0280E0_CB_COLOR0_FRAG + cb * 4,
+				0x00000000, 0xFFFFFFFF, bo[1]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_0280C0_CB_COLOR0_TILE + cb * 4,
+				0x00000000, 0xFFFFFFFF, bo[2]);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028100_CB_COLOR0_MASK + cb * 4,
+				0x00000000, 0xFFFFFFFF, NULL);
+}
+
+static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level;
+	unsigned pitch, slice, format;
+
+	if (state->zsbuf == NULL)
+		return;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tilled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	level = state->zsbuf->level;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02800C_DB_DEPTH_BASE,
+				state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028000_DB_DEPTH_SIZE,
+				S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028010_DB_DEPTH_INFO,
+				S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D34_DB_PREFETCH_LIMIT,
+				(state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
+}
+
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+					const struct pipe_framebuffer_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 shader_mask, tl, br, shader_control, target_mask;
+
+	if (rstate == NULL)
+		return;
+
+	/* unreference old buffer and reference new one */
+	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
+	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+		pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
+	}
+	pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
+	rctx->framebuffer = *state;
+
+	/* build states */
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		r600_cb(rctx, rstate, state, i);
+	}
+	if (state->zsbuf) {
+		r600_db(rctx, rstate, state);
+	}
+
+	target_mask = 0x00000000;
+	target_mask = 0xFFFFFFFF;
+	shader_mask = 0;
+	shader_control = 0;
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		target_mask ^= 0xf << (i * 4);
+		shader_mask |= 0xf << (i * 4);
+		shader_control |= 1 << i;
+	}
+	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
+				0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0287A0_CB_SHADER_CONTROL,
+				shader_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
+				0x00000000, target_mask, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
+				shader_mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C30_CB_CLRCMP_CONTROL,
+				0x01000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C34_CB_CLRCMP_SRC,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C38_CB_CLRCMP_DST,
+				0x000000FF, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C3C_CB_CLRCMP_MSK,
+				0xFFFFFFFF, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C48_PA_SC_AA_MASK,
+				0xFFFFFFFF, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
+	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_index_buffer(struct pipe_context *ctx,
+				  const struct pipe_index_buffer *ib)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	if (ib) {
+		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+	} else {
+		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+	}
+
+	/* TODO make this more like a state */
+}
+
+static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+					const struct pipe_vertex_buffer *buffers)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	for (int i = 0; i < rctx->nvertex_buffer; i++) {
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	}
+	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+	for (int i = 0; i < count; i++) {
+		rctx->vertex_buffer[i].buffer = NULL;
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	}
+	rctx->nvertex_buffer = count;
+}
+
+static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+					struct pipe_resource *buffer)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate;
+	struct pipe_transfer *transfer;
+	unsigned *nconst = NULL;
+	u32 *ptr, offset;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		rstate = rctx->vs_const;
+		nconst = &rctx->vs_nconst;
+		offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		rstate = rctx->ps_const;
+		nconst = &rctx->ps_nconst;
+		offset = R_030000_SQ_ALU_CONSTANT0_0;
+		break;
+	default:
+		R600_ERR("unsupported %d\n", shader);
+		return;
+	}
+	if (buffer && buffer->width0 > 0) {
+		*nconst = buffer->width0 / 16;
+		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
+		if (ptr == NULL)
+			return;
+		for (int i = 0; i < *nconst; i++, offset += 0x10) {
+			rstate[i].nregs = 0;
+			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
+			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
+			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
+			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
+			r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
+		}
+		pipe_buffer_unmap(ctx, buffer, transfer);
+	}
+}
+
+static void *r600_create_shader_state(struct pipe_context *ctx,
+					const struct pipe_shader_state *state)
+{
+	struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
+	int r;
+
+	r =  r600_pipe_shader_create2(ctx, shader, state->tokens);
+	if (r) {
+		return NULL;
+	}
+	return shader;
+}
+
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->ps_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->vs_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->ps_shader == shader) {
+		rctx->ps_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->vs_shader == shader) {
+		rctx->vs_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+static void r600_init_state_functions2(struct r600_pipe_context *rctx)
+{
+	rctx->context.create_blend_state = r600_create_blend_state;
+	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
+	rctx->context.create_fs_state = r600_create_shader_state;
+	rctx->context.create_rasterizer_state = r600_create_rs_state;
+	rctx->context.create_sampler_state = r600_create_sampler_state;
+	rctx->context.create_sampler_view = r600_create_sampler_view;
+	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
+	rctx->context.create_vs_state = r600_create_shader_state;
+	rctx->context.bind_blend_state = r600_bind_blend_state;
+	rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
+	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
+	rctx->context.bind_fs_state = r600_bind_ps_shader;
+	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
+	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
+	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
+	rctx->context.bind_vs_state = r600_bind_vs_shader;
+	rctx->context.delete_blend_state = r600_delete_state;
+	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
+	rctx->context.delete_fs_state = r600_delete_ps_shader;
+	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
+	rctx->context.delete_sampler_state = r600_delete_state;
+	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
+	rctx->context.delete_vs_state = r600_delete_vs_shader;
+	rctx->context.set_blend_color = r600_set_blend_color;
+	rctx->context.set_clip_state = r600_set_clip_state;
+	rctx->context.set_constant_buffer = r600_set_constant_buffer;
+	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
+	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
+	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
+	rctx->context.set_sample_mask = r600_set_sample_mask;
+	rctx->context.set_scissor_state = r600_set_scissor_state;
+	rctx->context.set_stencil_ref = r600_set_stencil_ref;
+	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+	rctx->context.set_index_buffer = r600_set_index_buffer;
+	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
+	rctx->context.set_viewport_state = r600_set_viewport_state;
+	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
+}
+
+static void r600_init_config2(struct r600_pipe_context *rctx)
+{
+	int ps_prio;
+	int vs_prio;
+	int gs_prio;
+	int es_prio;
+	int num_ps_gprs;
+	int num_vs_gprs;
+	int num_gs_gprs;
+	int num_es_gprs;
+	int num_temp_gprs;
+	int num_ps_threads;
+	int num_vs_threads;
+	int num_gs_threads;
+	int num_es_threads;
+	int num_ps_stack_entries;
+	int num_vs_stack_entries;
+	int num_gs_stack_entries;
+	int num_es_stack_entries;
+	enum radeon_family family;
+	struct r600_pipe_state *rstate = &rctx->config;
+	u32 tmp;
+
+	family = r600_get_family(rctx->radeon);
+	ps_prio = 0;
+	vs_prio = 1;
+	gs_prio = 2;
+	es_prio = 3;
+	switch (family) {
+	case CHIP_R600:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 40;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	default:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV670:
+		num_ps_gprs = 144;
+		num_vs_gprs = 40;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV770:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 256;
+		num_vs_stack_entries = 256;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV730:
+	case CHIP_RV740:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV710:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 48;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	}
+
+	rstate->id = R600_PIPE_STATE_CONFIG;
+
+	/* SQ_CONFIG */
+	tmp = 0;
+	switch (family) {
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV710:
+		break;
+	default:
+		tmp |= S_008C00_VC_ENABLE(1);
+		break;
+	}
+	tmp |= S_008C00_DX9_CONSTS(1);
+	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	tmp |= S_008C00_PS_PRIO(ps_prio);
+	tmp |= S_008C00_VS_PRIO(vs_prio);
+	tmp |= S_008C00_GS_PRIO(gs_prio);
+	tmp |= S_008C00_ES_PRIO(es_prio);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_GPR_RESOURCE_MGMT_1 */
+	tmp = 0;
+	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_GPR_RESOURCE_MGMT_2 */
+	tmp = 0;
+	tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_THREAD_RESOURCE_MGMT */
+	tmp = 0;
+	tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_STACK_RESOURCE_MGMT_1 */
+	tmp = 0;
+	tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_STACK_RESOURCE_MGMT_2 */
+	tmp = 0;
+	tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
+
+	if (family >= CHIP_RV770) {
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
+	} else {
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
+	}
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, 0x00FFFFFF, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
+{
+	struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
+	struct r600_screen* rscreen = (struct r600_screen *)screen;
+
+	if (rctx == NULL)
+		return NULL;
+	rctx->context.winsys = rscreen->screen.winsys;
+	rctx->context.screen = screen;
+	rctx->context.priv = priv;
+	rctx->context.destroy = r600_destroy_context;
+	rctx->context.draw_vbo = r600_draw_vbo2;
+	rctx->context.flush = r600_flush2;
+
+	/* Easy accessing of screen/winsys. */
+	rctx->screen = rscreen;
+	rctx->radeon = rscreen->radeon;
+
+	r600_init_blit_functions2(rctx);
+	r600_init_state_functions2(rctx);
+	r600_init_context_resource_functions2(rctx);
+
+	rctx->blitter = util_blitter_create(&rctx->context);
+	if (rctx->blitter == NULL) {
+		FREE(rctx);
+		return NULL;
+	}
+
+	if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	r600_init_config2(rctx);
+
+	return &rctx->context;
+}
+
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+	switch(shader)
+	{
+	case PIPE_SHADER_FRAGMENT:
+	case PIPE_SHADER_VERTEX:
+		break;
+	case PIPE_SHADER_GEOMETRY:
+		/* TODO: support and enable geometry programs */
+		return 0;
+	default:
+		/* TODO: support tessellation on Evergreen */
+		return 0;
+	}
+
+	/* TODO: all these should be fixed, since r600 surely supports much more! */
+	switch (param) {
+	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+		return 16384;
+	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+		return 8; /* FIXME */
+	case PIPE_SHADER_CAP_MAX_INPUTS:
+		if(shader == PIPE_SHADER_FRAGMENT)
+			return 10;
+		else
+			return 16;
+	case PIPE_SHADER_CAP_MAX_TEMPS:
+		return 256; //max native temporaries
+	case PIPE_SHADER_CAP_MAX_ADDRS:
+		return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
+	case PIPE_SHADER_CAP_MAX_CONSTS:
+		return 256; //max native parameters
+	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+		return 1;
+	case PIPE_SHADER_CAP_MAX_PREDS:
+		return 0; /* FIXME */
+	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+		/* TODO: support this! */
+		return 0;
+	default:
+		return 0;
+	}
+}
+
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
+struct pipe_screen *r600_screen_create2(struct radeon *radeon)
+{
+	struct r600_screen *rscreen;
+	enum radeon_family family = r600_get_family(radeon);
+
+	rscreen = CALLOC_STRUCT(r600_screen);
+	if (rscreen == NULL) {
+		return NULL;
+	}
+
+	switch (family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		rscreen->chip_class = R600;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		rscreen->chip_class = R700;
+		break;
+	default:
+		FREE(rscreen);
+		return NULL;
+	}
+	rscreen->radeon = radeon;
+	rscreen->screen.winsys = (struct pipe_winsys*)radeon;
+	rscreen->screen.destroy = r600_destroy_screen;
+	rscreen->screen.get_name = r600_get_name;
+	rscreen->screen.get_vendor = r600_get_vendor;
+	rscreen->screen.get_param = r600_get_param;
+	rscreen->screen.get_shader_param = r600_get_shader_param;
+	rscreen->screen.get_paramf = r600_get_paramf;
+	rscreen->screen.is_format_supported = r600_is_format_supported;
+	rscreen->screen.context_create = r600_create_context2;
+	r600_init_screen_texture_functions(&rscreen->screen);
+	r600_init_screen_resource_functions(&rscreen->screen);
+
+	return &rscreen->screen;
+}
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index efc5f820659..274679d1274 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -325,7 +325,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 	char *map;
 	int r;
 
-	r600_flush(ctx, 0, NULL);
+	ctx->flush(ctx, 0, NULL);
 	if (rtransfer->linear_texture) {
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index cd8acd20687..07bfc0593e9 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -124,13 +124,6 @@
 #define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
 #define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
 #define   C_008C04_NUM_CLAUSE_TEMP_GPRS(x)             0x0FFFFFFF
-#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x00008C08
-#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
-#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
-#define   C_008C08_NUM_GS_GPRS(x)                      0xFFFFFF00
-#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
-#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
-#define   C_008C08_NUM_ES_GPRS(x)                      0xFF00FFFF
 #define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x00008C0C
 #define   S_008C0C_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
 #define   G_008C0C_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
@@ -435,6 +428,22 @@
 #define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
 #define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
 #define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028414_CB_BLEND_RED                        0x028414
+#define   S_028414_BLEND_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028414_BLEND_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028414_BLEND_RED                           0x00000000
+#define R_028418_CB_BLEND_GREEN                      0x028418
+#define   S_028418_BLEND_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028418_BLEND_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028418_BLEND_GREEN                         0x00000000
+#define R_02841C_CB_BLEND_BLUE                       0x02841C
+#define   S_02841C_BLEND_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02841C_BLEND_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02841C_BLEND_BLUE                          0x00000000
+#define R_028420_CB_BLEND_ALPHA                      0x028420
+#define   S_028420_BLEND_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028420_BLEND_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028420_BLEND_ALPHA                         0x00000000
 #define R_028430_DB_STENCILREFMASK                   0x028430
 #define   S_028430_STENCILREF(x)                       (((x) & 0xFF) << 0)
 #define   G_028430_STENCILREF(x)                       (((x) >> 0) & 0xFF)
@@ -455,6 +464,14 @@
 #define   S_028434_STENCILWRITEMASK_BF(x)              (((x) & 0xFF) << 16)
 #define   G_028434_STENCILWRITEMASK_BF(x)              (((x) >> 16) & 0xFF)
 #define   C_028434_STENCILWRITEMASK_BF                 0xFF00FFFF
+#define R_028780_CB_BLEND0_CONTROL                   0x028780
+#define R_028784_CB_BLEND1_CONTROL                   0x028784
+#define R_028788_CB_BLEND2_CONTROL                   0x028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x02878C
+#define R_028790_CB_BLEND4_CONTROL                   0x028790
+#define R_028794_CB_BLEND5_CONTROL                   0x028794
+#define R_028798_CB_BLEND6_CONTROL                   0x028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x02879C
 #define R_028804_CB_BLEND_CONTROL                    0x028804
 #define   S_028804_COLOR_SRCBLEND(x)                   (((x) & 0x1F) << 0)
 #define   G_028804_COLOR_SRCBLEND(x)                   (((x) >> 0) & 0x1F)
@@ -1342,6 +1359,2081 @@
 #define   S_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) & 0x1) << 14)
 #define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
 #define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
+#define R_028084_CB_COLOR1_VIEW                      0x028084
+#define R_028088_CB_COLOR2_VIEW                      0x028088
+#define R_02808C_CB_COLOR3_VIEW                      0x02808C
+#define R_028090_CB_COLOR4_VIEW                      0x028090
+#define R_028094_CB_COLOR5_VIEW                      0x028094
+#define R_028098_CB_COLOR6_VIEW                      0x028098
+#define R_02809C_CB_COLOR7_VIEW                      0x02809C
+#define R_028104_CB_COLOR1_MASK                      0x028104
+#define R_028108_CB_COLOR2_MASK                      0x028108
+#define R_02810C_CB_COLOR3_MASK                      0x02810C
+#define R_028110_CB_COLOR4_MASK                      0x028110
+#define R_028114_CB_COLOR5_MASK                      0x028114
+#define R_028118_CB_COLOR6_MASK                      0x028118
+#define R_02811C_CB_COLOR7_MASK                      0x02811C
+#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
+#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
+#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
+#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
+#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
+#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
+#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
+#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
+#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
+#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
+#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
+#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
+#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
+#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
+#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
+#define R_028C30_CB_CLRCMP_CONTROL                   0x028C30
+#define   S_028C30_CLRCMP_FCN_SRC(x)                   (((x) & 0x7) << 0)
+#define   G_028C30_CLRCMP_FCN_SRC(x)                   (((x) >> 0) & 0x7)
+#define   C_028C30_CLRCMP_FCN_SRC                      0xFFFFFFF8
+#define   S_028C30_CLRCMP_FCN_DST(x)                   (((x) & 0x7) << 8)
+#define   G_028C30_CLRCMP_FCN_DST(x)                   (((x) >> 8) & 0x7)
+#define   C_028C30_CLRCMP_FCN_DST                      0xFFFFF8FF
+#define   S_028C30_CLRCMP_FCN_SEL(x)                   (((x) & 0x3) << 24)
+#define   G_028C30_CLRCMP_FCN_SEL(x)                   (((x) >> 24) & 0x3)
+#define   C_028C30_CLRCMP_FCN_SEL                      0xFCFFFFFF
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX    0x028C20
+#define   S_028C20_S4_X(x)                             (((x) & 0xF) << 0)
+#define   G_028C20_S4_X(x)                             (((x) >> 0) & 0xF)
+#define   C_028C20_S4_X                                0xFFFFFFF0
+#define   S_028C20_S4_Y(x)                             (((x) & 0xF) << 4)
+#define   G_028C20_S4_Y(x)                             (((x) >> 4) & 0xF)
+#define   C_028C20_S4_Y                                0xFFFFFF0F
+#define   S_028C20_S5_X(x)                             (((x) & 0xF) << 8)
+#define   G_028C20_S5_X(x)                             (((x) >> 8) & 0xF)
+#define   C_028C20_S5_X                                0xFFFFF0FF
+#define   S_028C20_S5_Y(x)                             (((x) & 0xF) << 12)
+#define   G_028C20_S5_Y(x)                             (((x) >> 12) & 0xF)
+#define   C_028C20_S5_Y                                0xFFFF0FFF
+#define   S_028C20_S6_X(x)                             (((x) & 0xF) << 16)
+#define   G_028C20_S6_X(x)                             (((x) >> 16) & 0xF)
+#define   C_028C20_S6_X                                0xFFF0FFFF
+#define   S_028C20_S6_Y(x)                             (((x) & 0xF) << 20)
+#define   G_028C20_S6_Y(x)                             (((x) >> 20) & 0xF)
+#define   C_028C20_S6_Y                                0xFF0FFFFF
+#define   S_028C20_S7_X(x)                             (((x) & 0xF) << 24)
+#define   G_028C20_S7_X(x)                             (((x) >> 24) & 0xF)
+#define   C_028C20_S7_X                                0xF0FFFFFF
+#define   S_028C20_S7_Y(x)                             (((x) & 0xF) << 28)
+#define   G_028C20_S7_Y(x)                             (((x) >> 28) & 0xF)
+#define   C_028C20_S7_Y                                0x0FFFFFFF
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_0280A0_ENDIAN                              0xFFFFFFFC
+#define   S_0280A0_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_0280A0_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_0280A0_FORMAT                              0xFFFFFF03
+#define     V_0280A0_COLOR_INVALID                     0x00000000
+#define     V_0280A0_COLOR_8                           0x00000001
+#define     V_0280A0_COLOR_4_4                         0x00000002
+#define     V_0280A0_COLOR_3_3_2                       0x00000003
+#define     V_0280A0_COLOR_16                          0x00000005
+#define     V_0280A0_COLOR_16_FLOAT                    0x00000006
+#define     V_0280A0_COLOR_8_8                         0x00000007
+#define     V_0280A0_COLOR_5_6_5                       0x00000008
+#define     V_0280A0_COLOR_6_5_5                       0x00000009
+#define     V_0280A0_COLOR_1_5_5_5                     0x0000000A
+#define     V_0280A0_COLOR_4_4_4_4                     0x0000000B
+#define     V_0280A0_COLOR_5_5_5_1                     0x0000000C
+#define     V_0280A0_COLOR_32                          0x0000000D
+#define     V_0280A0_COLOR_32_FLOAT                    0x0000000E
+#define     V_0280A0_COLOR_16_16                       0x0000000F
+#define     V_0280A0_COLOR_16_16_FLOAT                 0x00000010
+#define     V_0280A0_COLOR_8_24                        0x00000011
+#define     V_0280A0_COLOR_8_24_FLOAT                  0x00000012
+#define     V_0280A0_COLOR_24_8                        0x00000013
+#define     V_0280A0_COLOR_24_8_FLOAT                  0x00000014
+#define     V_0280A0_COLOR_10_11_11                    0x00000015
+#define     V_0280A0_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_0280A0_COLOR_11_11_10                    0x00000017
+#define     V_0280A0_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_0280A0_COLOR_2_10_10_10                  0x00000019
+#define     V_0280A0_COLOR_8_8_8_8                     0x0000001A
+#define     V_0280A0_COLOR_10_10_10_2                  0x0000001B
+#define     V_0280A0_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_0280A0_COLOR_32_32                       0x0000001D
+#define     V_0280A0_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_0280A0_COLOR_16_16_16_16                 0x0000001F
+#define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_0280A0_COLOR_32_32_32_32                 0x00000022
+#define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
+#define     V_0280A0_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_0280A0_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_0280A0_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_0280A0_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
+#define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
+#define   C_0280A0_READ_SIZE                           0xFFFF7FFF
+#define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
+#define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
+#define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
+#define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
+#define   C_0280A0_TILE_MODE                           0xFFF3FFFF
+#define   S_0280A0_BLEND_CLAMP(x)                      (((x) & 0x1) << 20)
+#define   G_0280A0_BLEND_CLAMP(x)                      (((x) >> 20) & 0x1)
+#define   C_0280A0_BLEND_CLAMP                         0xFFEFFFFF
+#define   S_0280A0_CLEAR_COLOR(x)                      (((x) & 0x1) << 21)
+#define   G_0280A0_CLEAR_COLOR(x)                      (((x) >> 21) & 0x1)
+#define   C_0280A0_CLEAR_COLOR                         0xFFDFFFFF
+#define   S_0280A0_BLEND_BYPASS(x)                     (((x) & 0x1) << 22)
+#define   G_0280A0_BLEND_BYPASS(x)                     (((x) >> 22) & 0x1)
+#define   C_0280A0_BLEND_BYPASS                        0xFFBFFFFF
+#define   S_0280A0_BLEND_FLOAT32(x)                    (((x) & 0x1) << 23)
+#define   G_0280A0_BLEND_FLOAT32(x)                    (((x) >> 23) & 0x1)
+#define   C_0280A0_BLEND_FLOAT32                       0xFF7FFFFF
+#define   S_0280A0_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 24)
+#define   G_0280A0_SIMPLE_FLOAT(x)                     (((x) >> 24) & 0x1)
+#define   C_0280A0_SIMPLE_FLOAT                        0xFEFFFFFF
+#define   S_0280A0_ROUND_MODE(x)                       (((x) & 0x1) << 25)
+#define   G_0280A0_ROUND_MODE(x)                       (((x) >> 25) & 0x1)
+#define   C_0280A0_ROUND_MODE                          0xFDFFFFFF
+#define   S_0280A0_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_0280A0_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_0280A0_TILE_COMPACT                        0xFBFFFFFF
+#define   S_0280A0_SOURCE_FORMAT(x)                    (((x) & 0x1) << 27)
+#define   G_0280A0_SOURCE_FORMAT(x)                    (((x) >> 27) & 0x1)
+#define   C_0280A0_SOURCE_FORMAT                       0xF7FFFFFF
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
+#define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
+#define   C_028010_FORMAT                              0xFFFFFFF8
+#define     V_028010_DEPTH_INVALID                     0x00000000
+#define     V_028010_DEPTH_16                          0x00000001
+#define     V_028010_DEPTH_X8_24                       0x00000002
+#define     V_028010_DEPTH_8_24                        0x00000003
+#define     V_028010_DEPTH_X8_24_FLOAT                 0x00000004
+#define     V_028010_DEPTH_8_24_FLOAT                  0x00000005
+#define     V_028010_DEPTH_32_FLOAT                    0x00000006
+#define     V_028010_DEPTH_X24_8_32_FLOAT              0x00000007
+#define   S_028010_READ_SIZE(x)                        (((x) & 0x1) << 3)
+#define   G_028010_READ_SIZE(x)                        (((x) >> 3) & 0x1)
+#define   C_028010_READ_SIZE                           0xFFFFFFF7
+#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)
+#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)
+#define   C_028010_ARRAY_MODE                          0xFFF87FFF
+#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)
+#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)
+#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF
+#define   S_028010_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_028010_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_028010_TILE_COMPACT                        0xFBFFFFFF
+#define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028000_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028000_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028000_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028000_SLICE_TILE_MAX                      0xC00003FF
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008DFC_SQ_CF_WORD0                         0x008DFC
+#define   S_008DFC_ADDR(x)                             (((x) & 0xFFFFFFFF) << 0)
+#define   G_008DFC_ADDR(x)                             (((x) >> 0) & 0xFFFFFFFF)
+#define   C_008DFC_ADDR                                0x00000000
+#define R_008DFC_SQ_CF_WORD1                         0x008DFC
+#define   S_008DFC_POP_COUNT(x)                        (((x) & 0x7) << 0)
+#define   G_008DFC_POP_COUNT(x)                        (((x) >> 0) & 0x7)
+#define   C_008DFC_POP_COUNT                           0xFFFFFFF8
+#define   S_008DFC_CF_CONST(x)                         (((x) & 0x1F) << 3)
+#define   G_008DFC_CF_CONST(x)                         (((x) >> 3) & 0x1F)
+#define   C_008DFC_CF_CONST                            0xFFFFFF07
+#define   S_008DFC_COND(x)                             (((x) & 0x3) << 8)
+#define   G_008DFC_COND(x)                             (((x) >> 8) & 0x3)
+#define   C_008DFC_COND                                0xFFFFFCFF
+#define   S_008DFC_COUNT(x)                            (((x) & 0x7) << 10)
+#define   G_008DFC_COUNT(x)                            (((x) >> 10) & 0x7)
+#define   C_008DFC_COUNT                               0xFFFFE3FF
+#define   S_008DFC_CALL_COUNT(x)                       (((x) & 0x3F) << 13)
+#define   G_008DFC_CALL_COUNT(x)                       (((x) >> 13) & 0x3F)
+#define   C_008DFC_CALL_COUNT                          0xFFF81FFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_NOP                    0x00000000
+#define     V_008DFC_SQ_CF_INST_TEX                    0x00000001
+#define     V_008DFC_SQ_CF_INST_VTX                    0x00000002
+#define     V_008DFC_SQ_CF_INST_VTX_TC                 0x00000003
+#define     V_008DFC_SQ_CF_INST_LOOP_START             0x00000004
+#define     V_008DFC_SQ_CF_INST_LOOP_END               0x00000005
+#define     V_008DFC_SQ_CF_INST_LOOP_START_DX10        0x00000006
+#define     V_008DFC_SQ_CF_INST_LOOP_START_NO_AL       0x00000007
+#define     V_008DFC_SQ_CF_INST_LOOP_CONTINUE          0x00000008
+#define     V_008DFC_SQ_CF_INST_LOOP_BREAK             0x00000009
+#define     V_008DFC_SQ_CF_INST_JUMP                   0x0000000A
+#define     V_008DFC_SQ_CF_INST_PUSH                   0x0000000B
+#define     V_008DFC_SQ_CF_INST_PUSH_ELSE              0x0000000C
+#define     V_008DFC_SQ_CF_INST_ELSE                   0x0000000D
+#define     V_008DFC_SQ_CF_INST_POP                    0x0000000E
+#define     V_008DFC_SQ_CF_INST_POP_JUMP               0x0000000F
+#define     V_008DFC_SQ_CF_INST_POP_PUSH               0x00000010
+#define     V_008DFC_SQ_CF_INST_POP_PUSH_ELSE          0x00000011
+#define     V_008DFC_SQ_CF_INST_CALL                   0x00000012
+#define     V_008DFC_SQ_CF_INST_CALL_FS                0x00000013
+#define     V_008DFC_SQ_CF_INST_RETURN                 0x00000014
+#define     V_008DFC_SQ_CF_INST_EMIT_VERTEX            0x00000015
+#define     V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX        0x00000016
+#define     V_008DFC_SQ_CF_INST_CUT_VERTEX             0x00000017
+#define     V_008DFC_SQ_CF_INST_KILL                   0x00000018
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD0                     0x008DFC
+#define   S_008DFC_ALU_ADDR(x)                         (((x) & 0x3FFFFF) << 0)
+#define   G_008DFC_ALU_ADDR(x)                         (((x) >> 0) & 0x3FFFFF)
+#define   C_008DFC_ALU_ADDR                            0xFFC00000
+#define   S_008DFC_KCACHE_BANK0(x)                     (((x) & 0xF) << 22)
+#define   G_008DFC_KCACHE_BANK0(x)                     (((x) >> 22) & 0xF)
+#define   C_008DFC_KCACHE_BANK0                        0xFC3FFFFF
+#define   S_008DFC_KCACHE_BANK1(x)                     (((x) & 0xF) << 26)
+#define   G_008DFC_KCACHE_BANK1(x)                     (((x) >> 26) & 0xF)
+#define   C_008DFC_KCACHE_BANK1                        0xC3FFFFFF
+#define   S_008DFC_KCACHE_MODE0(x)                     (((x) & 0x3) << 30)
+#define   G_008DFC_KCACHE_MODE0(x)                     (((x) >> 30) & 0x3)
+#define   C_008DFC_KCACHE_MODE0                        0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD1                     0x008DFC
+#define   S_008DFC_KCACHE_MODE1(x)                     (((x) & 0x3) << 0)
+#define   G_008DFC_KCACHE_MODE1(x)                     (((x) >> 0) & 0x3)
+#define   C_008DFC_KCACHE_MODE1                        0xFFFFFFFC
+#define   S_008DFC_KCACHE_ADDR0(x)                     (((x) & 0xFF) << 2)
+#define   G_008DFC_KCACHE_ADDR0(x)                     (((x) >> 2) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR0                        0xFFFFFC03
+#define   S_008DFC_KCACHE_ADDR1(x)                     (((x) & 0xFF) << 10)
+#define   G_008DFC_KCACHE_ADDR1(x)                     (((x) >> 10) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR1                        0xFFFC03FF
+#define   S_008DFC_ALU_COUNT(x)                        (((x) & 0x7F) << 18)
+#define   G_008DFC_ALU_COUNT(x)                        (((x) >> 18) & 0x7F)
+#define   C_008DFC_ALU_COUNT                           0xFE03FFFF
+#define   S_008DFC_USES_WATERFALL(x)                   (((x) & 0x1) << 25)
+#define   G_008DFC_USES_WATERFALL(x)                   (((x) >> 25) & 0x1)
+#define   C_008DFC_USES_WATERFALL                      0xFDFFFFFF
+#define   S_008DFC_CF_ALU_INST(x)                      (((x) & 0xF) << 26)
+#define   G_008DFC_CF_ALU_INST(x)                      (((x) >> 26) & 0xF)
+#define   C_008DFC_CF_ALU_INST                         0xC3FFFFFF
+#define     V_008DFC_SQ_CF_INST_ALU                    0x00000008
+#define     V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE        0x00000009
+#define     V_008DFC_SQ_CF_INST_ALU_POP_AFTER          0x0000000A
+#define     V_008DFC_SQ_CF_INST_ALU_POP2_AFTER         0x0000000B
+#define     V_008DFC_SQ_CF_INST_ALU_CONTINUE           0x0000000D
+#define     V_008DFC_SQ_CF_INST_ALU_BREAK              0x0000000E
+#define     V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER         0x0000000F
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0            0x008DFC
+#define   S_008DFC_ARRAY_BASE(x)                       (((x) & 0x1FFF) << 0)
+#define   G_008DFC_ARRAY_BASE(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_008DFC_ARRAY_BASE                          0xFFFFE000
+#define   S_008DFC_TYPE(x)                             (((x) & 0x3) << 13)
+#define   G_008DFC_TYPE(x)                             (((x) >> 13) & 0x3)
+#define   C_008DFC_TYPE                                0xFFFF9FFF
+#define   S_008DFC_RW_GPR(x)                           (((x) & 0x7F) << 15)
+#define   G_008DFC_RW_GPR(x)                           (((x) >> 15) & 0x7F)
+#define   C_008DFC_RW_GPR                              0xFFC07FFF
+#define   S_008DFC_RW_REL(x)                           (((x) & 0x1) << 22)
+#define   G_008DFC_RW_REL(x)                           (((x) >> 22) & 0x1)
+#define   C_008DFC_RW_REL                              0xFFBFFFFF
+#define   S_008DFC_INDEX_GPR(x)                        (((x) & 0x7F) << 23)
+#define   G_008DFC_INDEX_GPR(x)                        (((x) >> 23) & 0x7F)
+#define   C_008DFC_INDEX_GPR                           0xC07FFFFF
+#define   S_008DFC_ELEM_SIZE(x)                        (((x) & 0x3) << 30)
+#define   G_008DFC_ELEM_SIZE(x)                        (((x) >> 30) & 0x3)
+#define   C_008DFC_ELEM_SIZE                           0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1            0x008DFC
+#define   S_008DFC_BURST_COUNT(x)                      (((x) & 0xF) << 17)
+#define   G_008DFC_BURST_COUNT(x)                      (((x) >> 17) & 0xF)
+#define   C_008DFC_BURST_COUNT                         0xFFE1FFFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM0            0x00000020
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM1            0x00000021
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM2            0x00000022
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM3            0x00000023
+#define     V_008DFC_SQ_CF_INST_MEM_SCRATCH            0x00000024
+#define     V_008DFC_SQ_CF_INST_MEM_REDUCTION          0x00000025
+#define     V_008DFC_SQ_CF_INST_MEM_RING               0x00000026
+#define     V_008DFC_SQ_CF_INST_EXPORT                 0x00000027
+#define     V_008DFC_SQ_CF_INST_EXPORT_DONE            0x00000028
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF        0x008DFC
+#define   S_008DFC_ARRAY_SIZE(x)                       (((x) & 0xFFF) << 0)
+#define   G_008DFC_ARRAY_SIZE(x)                       (((x) >> 0) & 0xFFF)
+#define   C_008DFC_ARRAY_SIZE                          0xFFFFF000
+#define   S_008DFC_COMP_MASK(x)                        (((x) & 0xF) << 12)
+#define   G_008DFC_COMP_MASK(x)                        (((x) >> 12) & 0xF)
+#define   C_008DFC_COMP_MASK                           0xFFFF0FFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ       0x008DFC
+#define   S_008DFC_SEL_X(x)                            (((x) & 0x7) << 0)
+#define   G_008DFC_SEL_X(x)                            (((x) >> 0) & 0x7)
+#define   C_008DFC_SEL_X                               0xFFFFFFF8
+#define   S_008DFC_SEL_Y(x)                            (((x) & 0x7) << 3)
+#define   G_008DFC_SEL_Y(x)                            (((x) >> 3) & 0x7)
+#define   C_008DFC_SEL_Y                               0xFFFFFFC7
+#define   S_008DFC_SEL_Z(x)                            (((x) & 0x7) << 6)
+#define   G_008DFC_SEL_Z(x)                            (((x) >> 6) & 0x7)
+#define   C_008DFC_SEL_Z                               0xFFFFFE3F
+#define   S_008DFC_SEL_W(x)                            (((x) & 0x7) << 9)
+#define   G_008DFC_SEL_W(x)                            (((x) >> 9) & 0x7)
+#define   C_008DFC_SEL_W                               0xFFFFF1FF
+#define R_008DFC_SQ_VTX_WORD0                        0x008DFC
+#define   S_008DFC_VTX_INST(x)                         (((x) & 0x1F) << 0)
+#define   G_008DFC_VTX_INST(x)                         (((x) >> 0) & 0x1F)
+#define   C_008DFC_VTX_INST                            0xFFFFFFE0
+#define   S_008DFC_FETCH_TYPE(x)                       (((x) & 0x3) << 5)
+#define   G_008DFC_FETCH_TYPE(x)                       (((x) >> 5) & 0x3)
+#define   C_008DFC_FETCH_TYPE                          0xFFFFFF9F
+#define   S_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) & 0x1) << 7)
+#define   G_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) >> 7) & 0x1)
+#define   C_008DFC_FETCH_WHOLE_QUAD                    0xFFFFFF7F
+#define   S_008DFC_BUFFER_ID(x)                        (((x) & 0xFF) << 8)
+#define   G_008DFC_BUFFER_ID(x)                        (((x) >> 8) & 0xFF)
+#define   C_008DFC_BUFFER_ID                           0xFFFF00FF
+#define   S_008DFC_SRC_GPR(x)                          (((x) & 0x7F) << 16)
+#define   G_008DFC_SRC_GPR(x)                          (((x) >> 16) & 0x7F)
+#define   C_008DFC_SRC_GPR                             0xFF80FFFF
+#define   S_008DFC_SRC_REL(x)                          (((x) & 0x1) << 23)
+#define   G_008DFC_SRC_REL(x)                          (((x) >> 23) & 0x1)
+#define   C_008DFC_SRC_REL                             0xFF7FFFFF
+#define   S_008DFC_SRC_SEL_X(x)                        (((x) & 0x3) << 24)
+#define   G_008DFC_SRC_SEL_X(x)                        (((x) >> 24) & 0x3)
+#define   C_008DFC_SRC_SEL_X                           0xFCFFFFFF
+#define   S_008DFC_MEGA_FETCH_COUNT(x)                 (((x) & 0x3F) << 26)
+#define   G_008DFC_MEGA_FETCH_COUNT(x)                 (((x) >> 26) & 0x3F)
+#define   C_008DFC_MEGA_FETCH_COUNT                    0x03FFFFFF
+#define R_008DFC_SQ_VTX_WORD1                        0x008DFC
+#define   S_008DFC_DST_SEL_X(x)                        (((x) & 0x7) << 9)
+#define   G_008DFC_DST_SEL_X(x)                        (((x) >> 9) & 0x7)
+#define   C_008DFC_DST_SEL_X                           0xFFFFF1FF
+#define   S_008DFC_DST_SEL_Y(x)                        (((x) & 0x7) << 12)
+#define   G_008DFC_DST_SEL_Y(x)                        (((x) >> 12) & 0x7)
+#define   C_008DFC_DST_SEL_Y                           0xFFFF8FFF
+#define   S_008DFC_DST_SEL_Z(x)                        (((x) & 0x7) << 15)
+#define   G_008DFC_DST_SEL_Z(x)                        (((x) >> 15) & 0x7)
+#define   C_008DFC_DST_SEL_Z                           0xFFFC7FFF
+#define   S_008DFC_DST_SEL_W(x)                        (((x) & 0x7) << 18)
+#define   G_008DFC_DST_SEL_W(x)                        (((x) >> 18) & 0x7)
+#define   C_008DFC_DST_SEL_W                           0xFFE3FFFF
+#define   S_008DFC_USE_CONST_FIELDS(x)                 (((x) & 0x1) << 21)
+#define   G_008DFC_USE_CONST_FIELDS(x)                 (((x) >> 21) & 0x1)
+#define   C_008DFC_USE_CONST_FIELDS                    0xFFDFFFFF
+#define   S_008DFC_DATA_FORMAT(x)                      (((x) & 0x3F) << 22)
+#define   G_008DFC_DATA_FORMAT(x)                      (((x) >> 22) & 0x3F)
+#define   C_008DFC_DATA_FORMAT                         0xF03FFFFF
+#define   S_008DFC_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 28)
+#define   G_008DFC_NUM_FORMAT_ALL(x)                   (((x) >> 28) & 0x3)
+#define   C_008DFC_NUM_FORMAT_ALL                      0xCFFFFFFF
+#define   S_008DFC_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_FORMAT_COMP_ALL(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_FORMAT_COMP_ALL                     0xBFFFFFFF
+#define   S_008DFC_SRF_MODE_ALL(x)                     (((x) & 0x1) << 31)
+#define   G_008DFC_SRF_MODE_ALL(x)                     (((x) >> 31) & 0x1)
+#define   C_008DFC_SRF_MODE_ALL                        0x7FFFFFFF
+#define R_008DFC_SQ_VTX_WORD1_GPR                    0x008DFC
+#define   S_008DFC_DST_GPR(x)                          (((x) & 0x7F) << 0)
+#define   G_008DFC_DST_GPR(x)                          (((x) >> 0) & 0x7F)
+#define   C_008DFC_DST_GPR                             0xFFFFFF80
+#define   S_008DFC_DST_REL(x)                          (((x) & 0x1) << 7)
+#define   G_008DFC_DST_REL(x)                          (((x) >> 7) & 0x1)
+#define   C_008DFC_DST_REL                             0xFFFFFF7F
+#define R_008DFC_SQ_VTX_WORD2                        0x008DFC
+#define   S_008DFC_OFFSET(x)                           (((x) & 0xFFFF) << 0)
+#define   G_008DFC_OFFSET(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_OFFSET                              0xFFFF0000
+#define   S_008DFC_ENDIAN_SWAP(x)                      (((x) & 0x3) << 16)
+#define   G_008DFC_ENDIAN_SWAP(x)                      (((x) >> 16) & 0x3)
+#define   C_008DFC_ENDIAN_SWAP                         0xFFFCFFFF
+#define   S_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) & 0x1) << 18)
+#define   G_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) >> 18) & 0x1)
+#define   C_008DFC_CONST_BUF_NO_STRIDE                 0xFFFBFFFF
+#define   S_008DFC_MEGA_FETCH(x)                       (((x) & 0x1) << 19)
+#define   G_008DFC_MEGA_FETCH(x)                       (((x) >> 19) & 0x1)
+#define   C_008DFC_MEGA_FETCH                          0xFFF7FFFF
+#define   S_008DFC_ALT_CONST(x)                        (((x) & 0x1) << 20)
+#define   G_008DFC_ALT_CONST(x)                        (((x) >> 20) & 0x1)
+#define   C_008DFC_ALT_CONST                           0xFFEFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PARAM_GEN_ADDR(x)                   (((x) & 0x7F) << 19)
+#define   G_0286CC_PARAM_GEN_ADDR(x)                   (((x) >> 19) & 0x7F)
+#define   C_0286CC_PARAM_GEN_ADDR                      0xFC07FFFF
+#define   S_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) & 0x3) << 26)
+#define   G_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) >> 26) & 0x3)
+#define   C_0286CC_BARYC_SAMPLE_CNTL                   0xF3FFFFFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define   S_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) & 0x1) << 31)
+#define   G_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) >> 31) & 0x1)
+#define   C_0286CC_BARYC_AT_SAMPLE_ENA                 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_GEN_INDEX_PIX(x)                    (((x) & 0x1) << 0)
+#define   G_0286D0_GEN_INDEX_PIX(x)                    (((x) >> 0) & 0x1)
+#define   C_0286D0_GEN_INDEX_PIX                       0xFFFFFFFE
+#define   S_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) & 0x7F) << 1)
+#define   G_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) >> 1) & 0x7F)
+#define   C_0286D0_GEN_INDEX_PIX_ADDR                  0xFFFFFF01
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
+#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
+#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
+#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
+#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
+#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
+#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
+#define R_02800C_DB_DEPTH_BASE                       0x02800C
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
+#define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
+#define R_028C48_PA_SC_AA_MASK                       0x028C48
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define R_028820_PA_CL_NANINF_CNTL                   0x028820
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x028C18
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x028440
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x028448
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x028450
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x028254
+#define R_028780_CB_BLEND0_CONTROL                   0x028780
+#define R_028784_CB_BLEND1_CONTROL                   0x028784
+#define R_028788_CB_BLEND2_CONTROL                   0x028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x02878C
+#define R_028790_CB_BLEND4_CONTROL                   0x028790
+#define R_028794_CB_BLEND5_CONTROL                   0x028794
+#define R_028798_CB_BLEND6_CONTROL                   0x028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x02879C
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define R_028028_DB_STENCIL_CLEAR                    0x028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x02802C
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define R_02880C_DB_SHADER_CONTROL                   0x02880C
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define R_028D2C_DB_SRESULTS_COMPARE_STATE1          0x028D2C
+#define R_028D30_DB_PRELOAD_CONTROL                  0x028D30
+#define R_028D44_DB_ALPHA_TO_MASK                    0x028D44
+#define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x0286C0
+#define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
+#define R_028854_SQ_PGM_EXPORTS_PS                   0x028854
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define R_028A7C_VGT_DMA_INDEX_TYPE                  0x028A7C
+#define R_028A88_VGT_DMA_NUM_INSTANCES               0x028A88
+#define R_008970_VGT_NUM_INDICES                     0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define R_028238_CB_TARGET_MASK                      0x028238
+#define R_02823C_CB_SHADER_MASK                      0x02823C
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028064_CB_COLOR1_SIZE                      0x028064
+#define R_028068_CB_COLOR2_SIZE                      0x028068
+#define R_02806C_CB_COLOR3_SIZE                      0x02806C
+#define R_028070_CB_COLOR4_SIZE                      0x028070
+#define R_028074_CB_COLOR5_SIZE                      0x028074
+#define R_028078_CB_COLOR6_SIZE                      0x028078
+#define R_02807C_CB_COLOR7_SIZE                      0x02807C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define R_028044_CB_COLOR1_BASE                      0x028044
+#define R_028048_CB_COLOR2_BASE                      0x028048
+#define R_02804C_CB_COLOR3_BASE                      0x02804C
+#define R_028050_CB_COLOR4_BASE                      0x028050
+#define R_028054_CB_COLOR5_BASE                      0x028054
+#define R_028058_CB_COLOR6_BASE                      0x028058
+#define R_02805C_CB_COLOR7_BASE                      0x02805C
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define   S_028C04_MSAA_NUM_SAMPLES(x)                 (((x) & 0x3) << 0)
+#define   G_028C04_MSAA_NUM_SAMPLES(x)                 (((x) >> 0) & 0x3)
+#define   C_028C04_MSAA_NUM_SAMPLES                    0xFFFFFFFC
+#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
+#define   G_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) >> 4) & 0x1)
+#define   C_028C04_AA_MASK_CENTROID_DTMN               0xFFFFFFEF
+#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xF) << 13)
+#define   G_028C04_MAX_SAMPLE_DIST(x)                  (((x) >> 13) & 0xF)
+#define   C_028C04_MAX_SAMPLE_DIST                     0xFFFE1FFF
+#define R_0288CC_SQ_PGM_CF_OFFSET_PS                 0x0288CC
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define R_0288D0_SQ_PGM_CF_OFFSET_VS                 0x0288D0
+#define R_028840_SQ_PGM_START_PS                     0x028840
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define R_028858_SQ_PGM_START_VS                     0x028858
+#define R_028080_CB_COLOR0_VIEW                      0x028080
+#define   S_028080_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028080_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028080_SLICE_START                         0xFFFFF800
+#define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028080_SLICE_MAX                           0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW                      0x028084
+#define R_028088_CB_COLOR2_VIEW                      0x028088
+#define R_02808C_CB_COLOR3_VIEW                      0x02808C
+#define R_028090_CB_COLOR4_VIEW                      0x028090
+#define R_028094_CB_COLOR5_VIEW                      0x028094
+#define R_028098_CB_COLOR6_VIEW                      0x028098
+#define R_02809C_CB_COLOR7_VIEW                      0x02809C
+#define R_028100_CB_COLOR0_MASK                      0x028100
+#define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
+#define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
+#define   C_028100_CMASK_BLOCK_MAX                     0xFFFFF000
+#define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
+#define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
+#define   C_028100_FMASK_TILE_MAX                      0x00000FFF
+#define R_028104_CB_COLOR1_MASK                      0x028104
+#define R_028108_CB_COLOR2_MASK                      0x028108
+#define R_02810C_CB_COLOR3_MASK                      0x02810C
+#define R_028110_CB_COLOR4_MASK                      0x028110
+#define R_028114_CB_COLOR5_MASK                      0x028114
+#define R_028118_CB_COLOR6_MASK                      0x028118
+#define R_02811C_CB_COLOR7_MASK                      0x02811C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define   S_028040_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028040_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028040_BASE_256B                           0x00000000
+#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
+#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
+#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
+#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280C0_BASE_256B                           0x00000000
+#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
+#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
+#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
+#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
+#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
+#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
+#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028614_SPI_VS_OUT_ID_0                     0x028614
+#define   S_028614_SEMANTIC_0(x)                       (((x) & 0xFF) << 0)
+#define   G_028614_SEMANTIC_0(x)                       (((x) >> 0) & 0xFF)
+#define   C_028614_SEMANTIC_0                          0xFFFFFF00
+#define   S_028614_SEMANTIC_1(x)                       (((x) & 0xFF) << 8)
+#define   G_028614_SEMANTIC_1(x)                       (((x) >> 8) & 0xFF)
+#define   C_028614_SEMANTIC_1                          0xFFFF00FF
+#define   S_028614_SEMANTIC_2(x)                       (((x) & 0xFF) << 16)
+#define   G_028614_SEMANTIC_2(x)                       (((x) >> 16) & 0xFF)
+#define   C_028614_SEMANTIC_2                          0xFF00FFFF
+#define   S_028614_SEMANTIC_3(x)                       (((x) & 0xFF) << 24)
+#define   G_028614_SEMANTIC_3(x)                       (((x) >> 24) & 0xFF)
+#define   C_028614_SEMANTIC_3                          0x00FFFFFF
+#define R_028618_SPI_VS_OUT_ID_1                     0x028618
+#define R_02861C_SPI_VS_OUT_ID_2                     0x02861C
+#define R_028620_SPI_VS_OUT_ID_3                     0x028620
+#define R_028624_SPI_VS_OUT_ID_4                     0x028624
+#define R_028628_SPI_VS_OUT_ID_5                     0x028628
+#define R_02862C_SPI_VS_OUT_ID_6                     0x02862C
+#define R_028630_SPI_VS_OUT_ID_7                     0x028630
+#define R_028634_SPI_VS_OUT_ID_8                     0x028634
+#define R_028638_SPI_VS_OUT_ID_9                     0x028638
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define     V_038004_COLOR_INVALID                     0x00000000
+#define     V_038004_COLOR_8                           0x00000001
+#define     V_038004_COLOR_4_4                         0x00000002
+#define     V_038004_COLOR_3_3_2                       0x00000003
+#define     V_038004_COLOR_16                          0x00000005
+#define     V_038004_COLOR_16_FLOAT                    0x00000006
+#define     V_038004_COLOR_8_8                         0x00000007
+#define     V_038004_COLOR_5_6_5                       0x00000008
+#define     V_038004_COLOR_6_5_5                       0x00000009
+#define     V_038004_COLOR_1_5_5_5                     0x0000000A
+#define     V_038004_COLOR_4_4_4_4                     0x0000000B
+#define     V_038004_COLOR_5_5_5_1                     0x0000000C
+#define     V_038004_COLOR_32                          0x0000000D
+#define     V_038004_COLOR_32_FLOAT                    0x0000000E
+#define     V_038004_COLOR_16_16                       0x0000000F
+#define     V_038004_COLOR_16_16_FLOAT                 0x00000010
+#define     V_038004_COLOR_8_24                        0x00000011
+#define     V_038004_COLOR_8_24_FLOAT                  0x00000012
+#define     V_038004_COLOR_24_8                        0x00000013
+#define     V_038004_COLOR_24_8_FLOAT                  0x00000014
+#define     V_038004_COLOR_10_11_11                    0x00000015
+#define     V_038004_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_038004_COLOR_11_11_10                    0x00000017
+#define     V_038004_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_038004_COLOR_2_10_10_10                  0x00000019
+#define     V_038004_COLOR_8_8_8_8                     0x0000001A
+#define     V_038004_COLOR_10_10_10_2                  0x0000001B
+#define     V_038004_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_038004_COLOR_32_32                       0x0000001D
+#define     V_038004_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_038004_COLOR_16_16_16_16                 0x0000001F
+#define     V_038004_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_038004_COLOR_32_32_32_32                 0x00000022
+#define     V_038004_COLOR_32_32_32_32_FLOAT           0x00000023
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS                         0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS                         0xFF00FFFF
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x008D8C
+#define   S_008D8C_RING0_OFFSET(x)                     (((x) & 0xFF) << 0)
+#define   G_008D8C_RING0_OFFSET(x)                     (((x) >> 0) & 0xFF)
+#define   C_008D8C_RING0_OFFSET                        0xFFFFFF00
+#define   S_008D8C_ISOLATE_ES_ENABLE(x)                (((x) & 0x1) << 12)
+#define   G_008D8C_ISOLATE_ES_ENABLE(x)                (((x) >> 12) & 0x1)
+#define   C_008D8C_ISOLATE_ES_ENABLE                   0xFFFFEFFF
+#define   S_008D8C_ISOLATE_GS_ENABLE(x)                (((x) & 0x1) << 13)
+#define   G_008D8C_ISOLATE_GS_ENABLE(x)                (((x) >> 13) & 0x1)
+#define   C_008D8C_ISOLATE_GS_ENABLE                   0xFFFFDFFF
+#define   S_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) & 0x1) << 14)
+#define   G_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) >> 14) & 0x1)
+#define   C_008D8C_VS_PC_LIMIT_ENABLE                  0xFFFFBFFF
+#define R_009508_TA_CNTL_AUX                         0x009508
+#define   S_009508_DISABLE_CUBE_WRAP(x)                (((x) & 0x1) << 0)
+#define   G_009508_DISABLE_CUBE_WRAP(x)                (((x) >> 0) & 0x1)
+#define   C_009508_DISABLE_CUBE_WRAP                   0xFFFFFFFE
+#define   S_009508_SYNC_GRADIENT(x)                    (((x) & 0x1) << 24)
+#define   G_009508_SYNC_GRADIENT(x)                    (((x) >> 24) & 0x1)
+#define   C_009508_SYNC_GRADIENT                       0xFEFFFFFF
+#define   S_009508_SYNC_WALKER(x)                      (((x) & 0x1) << 25)
+#define   G_009508_SYNC_WALKER(x)                      (((x) >> 25) & 0x1)
+#define   C_009508_SYNC_WALKER                         0xFDFFFFFF
+#define   S_009508_SYNC_ALIGNER(x)                     (((x) & 0x1) << 26)
+#define   G_009508_SYNC_ALIGNER(x)                     (((x) >> 26) & 0x1)
+#define   C_009508_SYNC_ALIGNER                        0xFBFFFFFF
+#define   S_009508_BILINEAR_PRECISION(x)               (((x) & 0x1) << 31)
+#define   G_009508_BILINEAR_PRECISION(x)               (((x) >> 31) & 0x1)
+#define   C_009508_BILINEAR_PRECISION                  0x7FFFFFFF
+#define R_009714_VC_ENHANCE                          0x009714
+#define R_009830_DB_DEBUG                            0x009830
+#define R_009838_DB_WATERMARKS                       0x009838
+#define   S_009838_DEPTH_FREE(x)                       (((x) & 0x1F) << 0)
+#define   G_009838_DEPTH_FREE(x)                       (((x) >> 0) & 0x1F)
+#define   C_009838_DEPTH_FREE                          0xFFFFFFE0
+#define   S_009838_DEPTH_FLUSH(x)                      (((x) & 0x3F) << 5)
+#define   G_009838_DEPTH_FLUSH(x)                      (((x) >> 5) & 0x3F)
+#define   C_009838_DEPTH_FLUSH                         0xFFFFF81F
+#define   S_009838_FORCE_SUMMARIZE(x)                  (((x) & 0xF) << 11)
+#define   G_009838_FORCE_SUMMARIZE(x)                  (((x) >> 11) & 0xF)
+#define   C_009838_FORCE_SUMMARIZE                     0xFFFF87FF
+#define   S_009838_DEPTH_PENDING_FREE(x)               (((x) & 0x1F) << 15)
+#define   G_009838_DEPTH_PENDING_FREE(x)               (((x) >> 15) & 0x1F)
+#define   C_009838_DEPTH_PENDING_FREE                  0xFFF07FFF
+#define   S_009838_DEPTH_CACHELINE_FREE(x)             (((x) & 0x1F) << 20)
+#define   G_009838_DEPTH_CACHELINE_FREE(x)             (((x) >> 20) & 0x1F)
+#define   C_009838_DEPTH_CACHELINE_FREE                0xFE0FFFFF
+#define   S_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) & 0x1) << 25)
+#define   G_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) >> 25) & 0x1)
+#define   C_009838_EARLY_Z_PANIC_DISABLE               0xFDFFFFFF
+#define   S_009838_LATE_Z_PANIC_DISABLE(x)             (((x) & 0x1) << 26)
+#define   G_009838_LATE_Z_PANIC_DISABLE(x)             (((x) >> 26) & 0x1)
+#define   C_009838_LATE_Z_PANIC_DISABLE                0xFBFFFFFF
+#define   S_009838_RE_Z_PANIC_DISABLE(x)               (((x) & 0x1) << 27)
+#define   G_009838_RE_Z_PANIC_DISABLE(x)               (((x) >> 27) & 0x1)
+#define   C_009838_RE_Z_PANIC_DISABLE                  0xF7FFFFFF
+#define   S_009838_DB_EXTRA_DEBUG(x)                   (((x) & 0xF) << 28)
+#define   G_009838_DB_EXTRA_DEBUG(x)                   (((x) >> 28) & 0xF)
+#define   C_009838_DB_EXTRA_DEBUG                      0x0FFFFFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x028200
+#define   S_028200_WINDOW_X_OFFSET(x)                  (((x) & 0x7FFF) << 0)
+#define   G_028200_WINDOW_X_OFFSET(x)                  (((x) >> 0) & 0x7FFF)
+#define   C_028200_WINDOW_X_OFFSET                     0xFFFF8000
+#define   S_028200_WINDOW_Y_OFFSET(x)                  (((x) & 0x7FFF) << 16)
+#define   G_028200_WINDOW_Y_OFFSET(x)                  (((x) >> 16) & 0x7FFF)
+#define   C_028200_WINDOW_Y_OFFSET                     0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x02820C
+#define   S_02820C_CLIP_RULE(x)                        (((x) & 0xFFFF) << 0)
+#define   G_02820C_CLIP_RULE(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_02820C_CLIP_RULE                           0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x028210
+#define   S_028210_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028210_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028210_TL_X                                0xFFFFC000
+#define   S_028210_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028210_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028210_TL_Y                                0xC000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x028214
+#define   S_028214_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028214_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028214_BR_X                                0xFFFFC000
+#define   S_028214_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028214_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028214_BR_Y                                0xC000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x02822C
+#define R_028230_PA_SC_EDGERULE                      0x028230
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x0282D0
+#define   S_0282D0_VPORT_ZMIN(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D0_VPORT_ZMIN(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D0_VPORT_ZMIN                          0x00000000
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x0282D4
+#define   S_0282D4_VPORT_ZMAX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D4_VPORT_ZMAX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D4_VPORT_ZMAX                          0x00000000
+#define R_028350_SX_MISC                             0x028350
+#define   S_028350_MULTIPASS(x)                        (((x) & 0x1) << 0)
+#define   G_028350_MULTIPASS(x)                        (((x) >> 0) & 0x1)
+#define   C_028350_MULTIPASS                           0xFFFFFFFE
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x028380
+#define   S_028380_SEMANTIC_ID(x)                      (((x) & 0xFF) << 0)
+#define   G_028380_SEMANTIC_ID(x)                      (((x) >> 0) & 0xFF)
+#define   C_028380_SEMANTIC_ID                         0xFFFFFF00
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x02838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x02839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x0283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x0283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x0283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x0283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x0283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x0283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x0283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x0283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x0283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x0283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x0283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x0283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x0283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x0283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x0283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x0283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x0283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x0283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x0283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x0283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x0283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x0283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x0283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x0283FC
+#define R_028400_VGT_MAX_VTX_INDX                    0x028400
+#define   S_028400_MAX_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028400_MAX_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028400_MAX_INDX                            0x00000000
+#define R_028404_VGT_MIN_VTX_INDX                    0x028404
+#define   S_028404_MIN_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028404_MIN_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028404_MIN_INDX                            0x00000000
+#define R_028408_VGT_INDX_OFFSET                     0x028408
+#define   S_028408_INDX_OFFSET(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028408_INDX_OFFSET(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028408_INDX_OFFSET                         0x00000000
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x02840C
+#define   S_02840C_RESET_INDX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02840C_RESET_INDX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02840C_RESET_INDX                          0x00000000
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+#define R_028414_CB_BLEND_RED                        0x028414
+#define   S_028414_BLEND_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028414_BLEND_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028414_BLEND_RED                           0x00000000
+#define R_028418_CB_BLEND_GREEN                      0x028418
+#define   S_028418_BLEND_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028418_BLEND_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028418_BLEND_GREEN                         0x00000000
+#define R_02841C_CB_BLEND_BLUE                       0x02841C
+#define   S_02841C_BLEND_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02841C_BLEND_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02841C_BLEND_BLUE                          0x00000000
+#define R_028420_CB_BLEND_ALPHA                      0x028420
+#define   S_028420_BLEND_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028420_BLEND_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028420_BLEND_ALPHA                         0x00000000
+#define R_028438_SX_ALPHA_REF                        0x028438
+#define   S_028438_ALPHA_REF(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028438_ALPHA_REF(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028438_ALPHA_REF                           0x00000000
+#define R_0286C8_SPI_THREAD_GROUPING                 0x0286C8
+#define   S_0286C8_PS_GROUPING(x)                      (((x) & 0x1F) << 0)
+#define   G_0286C8_PS_GROUPING(x)                      (((x) >> 0) & 0x1F)
+#define   C_0286C8_PS_GROUPING                         0xFFFFFFE0
+#define   S_0286C8_VS_GROUPING(x)                      (((x) & 0x1F) << 8)
+#define   G_0286C8_VS_GROUPING(x)                      (((x) >> 8) & 0x1F)
+#define   C_0286C8_VS_GROUPING                         0xFFFFE0FF
+#define   S_0286C8_GS_GROUPING(x)                      (((x) & 0x1F) << 16)
+#define   G_0286C8_GS_GROUPING(x)                      (((x) >> 16) & 0x1F)
+#define   C_0286C8_GS_GROUPING                         0xFFE0FFFF
+#define   S_0286C8_ES_GROUPING(x)                      (((x) & 0x1F) << 24)
+#define   G_0286C8_ES_GROUPING(x)                      (((x) >> 24) & 0x1F)
+#define   C_0286C8_ES_GROUPING                         0xE0FFFFFF
+#define R_0286D8_SPI_INPUT_Z                         0x0286D8
+#define   S_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) & 0x1) << 0)
+#define   G_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) >> 0) & 0x1)
+#define   C_0286D8_PROVIDE_Z_TO_SPI                    0xFFFFFFFE
+#define R_0286DC_SPI_FOG_CNTL                        0x0286DC
+#define   S_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) & 0x1) << 0)
+#define   G_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) >> 0) & 0x1)
+#define   C_0286DC_PASS_FOG_THROUGH_PS                 0xFFFFFFFE
+#define   S_0286DC_PIXEL_FOG_FUNC(x)                   (((x) & 0x3) << 1)
+#define   G_0286DC_PIXEL_FOG_FUNC(x)                   (((x) >> 1) & 0x3)
+#define   C_0286DC_PIXEL_FOG_FUNC                      0xFFFFFFF9
+#define   S_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) & 0x1) << 3)
+#define   G_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) >> 3) & 0x1)
+#define   C_0286DC_PIXEL_FOG_SRC_SEL                   0xFFFFFFF7
+#define   S_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) & 0x1) << 4)
+#define   G_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) >> 4) & 0x1)
+#define   C_0286DC_VS_FOG_CLAMP_DISABLE                0xFFFFFFEF
+#define R_0286E0_SPI_FOG_FUNC_SCALE                  0x0286E0
+#define   S_0286E0_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E0_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E0_VALUE                               0x00000000
+#define R_0286E4_SPI_FOG_FUNC_BIAS                   0x0286E4
+#define   S_0286E4_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E4_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E4_VALUE                               0x00000000
+#define R_0287A0_CB_SHADER_CONTROL                   0x0287A0
+#define   S_0287A0_RT0_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_0287A0_RT0_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_0287A0_RT0_ENABLE                          0xFFFFFFFE
+#define   S_0287A0_RT1_ENABLE(x)                       (((x) & 0x1) << 1)
+#define   G_0287A0_RT1_ENABLE(x)                       (((x) >> 1) & 0x1)
+#define   C_0287A0_RT1_ENABLE                          0xFFFFFFFD
+#define   S_0287A0_RT2_ENABLE(x)                       (((x) & 0x1) << 2)
+#define   G_0287A0_RT2_ENABLE(x)                       (((x) >> 2) & 0x1)
+#define   C_0287A0_RT2_ENABLE                          0xFFFFFFFB
+#define   S_0287A0_RT3_ENABLE(x)                       (((x) & 0x1) << 3)
+#define   G_0287A0_RT3_ENABLE(x)                       (((x) >> 3) & 0x1)
+#define   C_0287A0_RT3_ENABLE                          0xFFFFFFF7
+#define   S_0287A0_RT4_ENABLE(x)                       (((x) & 0x1) << 4)
+#define   G_0287A0_RT4_ENABLE(x)                       (((x) >> 4) & 0x1)
+#define   C_0287A0_RT4_ENABLE                          0xFFFFFFEF
+#define   S_0287A0_RT5_ENABLE(x)                       (((x) & 0x1) << 5)
+#define   G_0287A0_RT5_ENABLE(x)                       (((x) >> 5) & 0x1)
+#define   C_0287A0_RT5_ENABLE                          0xFFFFFFDF
+#define   S_0287A0_RT6_ENABLE(x)                       (((x) & 0x1) << 6)
+#define   G_0287A0_RT6_ENABLE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287A0_RT6_ENABLE                          0xFFFFFFBF
+#define   S_0287A0_RT7_ENABLE(x)                       (((x) & 0x1) << 7)
+#define   G_0287A0_RT7_ENABLE(x)                       (((x) >> 7) & 0x1)
+#define   C_0287A0_RT7_ENABLE                          0xFFFFFF7F
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define   S_028894_PGM_START(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028894_PGM_START(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028894_PGM_START                           0x00000000
+#define R_0288A4_SQ_PGM_RESOURCES_FS                 0x0288A4
+#define   S_0288A4_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_0288A4_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_0288A4_NUM_GPRS                            0xFFFFFF00
+#define   S_0288A4_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_0288A4_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_0288A4_STACK_SIZE                          0xFFFF00FF
+#define   S_0288A4_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_0288A4_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_0288A4_DX10_CLAMP                          0xFFDFFFFF
+#define R_0288A8_SQ_ESGS_RING_ITEMSIZE               0x0288A8
+#define   S_0288A8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288A8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288A8_ITEMSIZE                            0xFFFF8000
+#define R_0288AC_SQ_GSVS_RING_ITEMSIZE               0x0288AC
+#define   S_0288AC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288AC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288AC_ITEMSIZE                            0xFFFF8000
+#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE              0x0288B0
+#define   S_0288B0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B0_ITEMSIZE                            0xFFFF8000
+#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE              0x0288B4
+#define   S_0288B4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B4_ITEMSIZE                            0xFFFF8000
+#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE              0x0288B8
+#define   S_0288B8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B8_ITEMSIZE                            0xFFFF8000
+#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE              0x0288BC
+#define   S_0288BC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288BC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288BC_ITEMSIZE                            0xFFFF8000
+#define R_0288C0_SQ_FBUF_RING_ITEMSIZE               0x0288C0
+#define   S_0288C0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C0_ITEMSIZE                            0xFFFF8000
+#define R_0288C4_SQ_REDUC_RING_ITEMSIZE              0x0288C4
+#define   S_0288C4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C4_ITEMSIZE                            0xFFFF8000
+#define R_0288C8_SQ_GS_VERT_ITEMSIZE                 0x0288C8
+#define   S_0288C8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C8_ITEMSIZE                            0xFFFF8000
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define   S_0288DC_PGM_CF_OFFSET(x)                    (((x) & 0xFFFFF) << 0)
+#define   G_0288DC_PGM_CF_OFFSET(x)                    (((x) >> 0) & 0xFFFFF)
+#define   C_0288DC_PGM_CF_OFFSET                       0xFFF00000
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x028A10
+#define   S_028A10_PATH_SELECT(x)                      (((x) & 0x3) << 0)
+#define   G_028A10_PATH_SELECT(x)                      (((x) >> 0) & 0x3)
+#define   C_028A10_PATH_SELECT                         0xFFFFFFFC
+#define R_028A14_VGT_HOS_CNTL                        0x028A14
+#define   S_028A14_TESS_MODE(x)                        (((x) & 0x3) << 0)
+#define   G_028A14_TESS_MODE(x)                        (((x) >> 0) & 0x3)
+#define   C_028A14_TESS_MODE                           0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x028A18
+#define   S_028A18_MAX_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A18_MAX_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A18_MAX_TESS                            0x00000000
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x028A1C
+#define   S_028A1C_MIN_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A1C_MIN_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A1C_MIN_TESS                            0x00000000
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x028A20
+#define   S_028A20_REUSE_DEPTH(x)                      (((x) & 0xFF) << 0)
+#define   G_028A20_REUSE_DEPTH(x)                      (((x) >> 0) & 0xFF)
+#define   C_028A20_REUSE_DEPTH                         0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x028A24
+#define   S_028A24_PRIM_TYPE(x)                        (((x) & 0x1F) << 0)
+#define   G_028A24_PRIM_TYPE(x)                        (((x) >> 0) & 0x1F)
+#define   C_028A24_PRIM_TYPE                           0xFFFFFFE0
+#define   S_028A24_RETAIN_ORDER(x)                     (((x) & 0x1) << 14)
+#define   G_028A24_RETAIN_ORDER(x)                     (((x) >> 14) & 0x1)
+#define   C_028A24_RETAIN_ORDER                        0xFFFFBFFF
+#define   S_028A24_RETAIN_QUADS(x)                     (((x) & 0x1) << 15)
+#define   G_028A24_RETAIN_QUADS(x)                     (((x) >> 15) & 0x1)
+#define   C_028A24_RETAIN_QUADS                        0xFFFF7FFF
+#define   S_028A24_PRIM_ORDER(x)                       (((x) & 0x7) << 16)
+#define   G_028A24_PRIM_ORDER(x)                       (((x) >> 16) & 0x7)
+#define   C_028A24_PRIM_ORDER                          0xFFF8FFFF
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x028A28
+#define   S_028A28_FIRST_DECR(x)                       (((x) & 0xF) << 0)
+#define   G_028A28_FIRST_DECR(x)                       (((x) >> 0) & 0xF)
+#define   C_028A28_FIRST_DECR                          0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR                      0x028A2C
+#define   S_028A2C_DECR(x)                             (((x) & 0xF) << 0)
+#define   G_028A2C_DECR(x)                             (((x) >> 0) & 0xF)
+#define   C_028A2C_DECR                                0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x028A30
+#define   S_028A30_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A30_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A30_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A30_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A30_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A30_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A30_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A30_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A30_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A30_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A30_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A30_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A30_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A30_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A30_STRIDE                              0xFFFF00FF
+#define   S_028A30_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A30_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A30_SHIFT                               0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x028A34
+#define   S_028A34_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A34_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A34_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A34_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A34_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A34_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A34_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A34_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A34_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A34_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A34_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A34_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A34_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A34_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A34_STRIDE                              0xFFFF00FF
+#define   S_028A34_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A34_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A34_SHIFT                               0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x028A38
+#define   S_028A38_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A38_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A38_X_CONV                              0xFFFFFFF0
+#define   S_028A38_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A38_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A38_X_OFFSET                            0xFFFFFF0F
+#define   S_028A38_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A38_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A38_Y_CONV                              0xFFFFF0FF
+#define   S_028A38_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A38_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A38_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A38_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A38_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A38_Z_CONV                              0xFFF0FFFF
+#define   S_028A38_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A38_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A38_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A38_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A38_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A38_W_CONV                              0xF0FFFFFF
+#define   S_028A38_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A38_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A38_W_OFFSET                            0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x028A3C
+#define   S_028A3C_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A3C_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A3C_X_CONV                              0xFFFFFFF0
+#define   S_028A3C_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A3C_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A3C_X_OFFSET                            0xFFFFFF0F
+#define   S_028A3C_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A3C_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A3C_Y_CONV                              0xFFFFF0FF
+#define   S_028A3C_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A3C_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A3C_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A3C_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A3C_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A3C_Z_CONV                              0xFFF0FFFF
+#define   S_028A3C_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A3C_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A3C_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A3C_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A3C_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A3C_W_CONV                              0xF0FFFFFF
+#define   S_028A3C_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A3C_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A3C_W_OFFSET                            0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_028A4C_PA_SC_MODE_CNTL                     0x028A4C
+#define   S_028A4C_MSAA_ENABLE(x)                      (((x) & 0x1) << 0)
+#define   G_028A4C_MSAA_ENABLE(x)                      (((x) >> 0) & 0x1)
+#define   C_028A4C_MSAA_ENABLE                         0xFFFFFFFE
+#define   S_028A4C_CLIPRECT_ENABLE(x)                  (((x) & 0x1) << 1)
+#define   G_028A4C_CLIPRECT_ENABLE(x)                  (((x) >> 1) & 0x1)
+#define   C_028A4C_CLIPRECT_ENABLE                     0xFFFFFFFD
+#define   S_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) & 0x1) << 2)
+#define   G_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) >> 2) & 0x1)
+#define   C_028A4C_LINE_STIPPLE_ENABLE                 0xFFFFFFFB
+#define   S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) & 0x1) << 3)
+#define   G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) >> 3) & 0x1)
+#define   C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB        0xFFFFFFF7
+#define   S_028A4C_WALK_ORDER_ENABLE(x)                (((x) & 0x1) << 4)
+#define   G_028A4C_WALK_ORDER_ENABLE(x)                (((x) >> 4) & 0x1)
+#define   C_028A4C_WALK_ORDER_ENABLE                   0xFFFFFFEF
+#define   S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) & 0x1) << 5)
+#define   G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) >> 5) & 0x1)
+#define   C_028A4C_HALVE_DETAIL_SAMPLE_PERF            0xFFFFFFDF
+#define   S_028A4C_WALK_SIZE(x)                        (((x) & 0x1) << 6)
+#define   G_028A4C_WALK_SIZE(x)                        (((x) >> 6) & 0x1)
+#define   C_028A4C_WALK_SIZE                           0xFFFFFFBF
+#define   S_028A4C_WALK_ALIGNMENT(x)                   (((x) & 0x1) << 7)
+#define   G_028A4C_WALK_ALIGNMENT(x)                   (((x) >> 7) & 0x1)
+#define   C_028A4C_WALK_ALIGNMENT                      0xFFFFFF7F
+#define   S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) & 0x1) << 8)
+#define   G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) >> 8) & 0x1)
+#define   C_028A4C_WALK_ALIGN8_PRIM_FITS_ST            0xFFFFFEFF
+#define   S_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) & 0x1) << 9)
+#define   G_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) >> 9) & 0x1)
+#define   C_028A4C_TILE_COVER_NO_SCISSOR               0xFFFFFDFF
+#define   S_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) & 0x1) << 10)
+#define   G_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) >> 10) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_HI_Z                  0xFFFFFBFF
+#define   S_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) & 0x1) << 11)
+#define   G_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) >> 11) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_DETAIL_MASK           0xFFFFF7FF
+#define   S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) & 0x1) << 12)
+#define   G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) >> 12) & 0x1)
+#define   C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE         0xFFFFEFFF
+#define   S_028A4C_TILE_COVER_DISABLE(x)               (((x) & 0x1) << 13)
+#define   G_028A4C_TILE_COVER_DISABLE(x)               (((x) >> 13) & 0x1)
+#define   C_028A4C_TILE_COVER_DISABLE                  0xFFFFDFFF
+#define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) & 0x1) << 14)
+#define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) >> 14) & 0x1)
+#define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE             0xFFFFBFFF
+#define   S_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) & 0x1) << 15)
+#define   G_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) >> 15) & 0x1)
+#define   C_028A4C_FORCE_EOV_TILE_ENABLE               0xFFFF7FFF
+#define   S_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) & 0x1) << 16)
+#define   G_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) >> 16) & 0x1)
+#define   C_028A4C_FORCE_EOV_REZ_ENABLE                0xFFFEFFFF
+#define   S_028A4C_PS_ITER_SAMPLE(x)                   (((x) & 0x1) << 17)
+#define   G_028A4C_PS_ITER_SAMPLE(x)                   (((x) >> 17) & 0x1)
+#define   C_028A4C_PS_ITER_SAMPLE                      0xFFFDFFFF
+#define R_028A84_VGT_PRIMITIVEID_EN                  0x028A84
+#define   S_028A84_PRIMITIVEID_EN(x)                   (((x) & 0x1) << 0)
+#define   G_028A84_PRIMITIVEID_EN(x)                   (((x) >> 0) & 0x1)
+#define   C_028A84_PRIMITIVEID_EN                      0xFFFFFFFE
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN          0x028A94
+#define   S_028A94_RESET_EN(x)                         (((x) & 0x1) << 0)
+#define   G_028A94_RESET_EN(x)                         (((x) >> 0) & 0x1)
+#define   C_028A94_RESET_EN                            0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0            0x028AA0
+#define   S_028AA0_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA0_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA0_STEP_RATE                           0x00000000
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1            0x028AA4
+#define   S_028AA4_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA4_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA4_STEP_RATE                           0x00000000
+#define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
+#define   S_028AB0_STREAMOUT(x)                        (((x) & 0x1) << 0)
+#define   G_028AB0_STREAMOUT(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB0_STREAMOUT                           0xFFFFFFFE
+#define R_028AB4_VGT_REUSE_OFF                       0x028AB4
+#define   S_028AB4_REUSE_OFF(x)                        (((x) & 0x1) << 0)
+#define   G_028AB4_REUSE_OFF(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB4_REUSE_OFF                           0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN                      0x028AB8
+#define   S_028AB8_VTX_CNT_EN(x)                       (((x) & 0x1) << 0)
+#define   G_028AB8_VTX_CNT_EN(x)                       (((x) >> 0) & 0x1)
+#define   C_028AB8_VTX_CNT_EN                          0xFFFFFFFE
+#define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
+#define   S_028B20_BUFFER_0_EN(x)                      (((x) & 0x1) << 0)
+#define   G_028B20_BUFFER_0_EN(x)                      (((x) >> 0) & 0x1)
+#define   C_028B20_BUFFER_0_EN                         0xFFFFFFFE
+#define   S_028B20_BUFFER_1_EN(x)                      (((x) & 0x1) << 1)
+#define   G_028B20_BUFFER_1_EN(x)                      (((x) >> 1) & 0x1)
+#define   C_028B20_BUFFER_1_EN                         0xFFFFFFFD
+#define   S_028B20_BUFFER_2_EN(x)                      (((x) & 0x1) << 2)
+#define   G_028B20_BUFFER_2_EN(x)                      (((x) >> 2) & 0x1)
+#define   C_028B20_BUFFER_2_EN                         0xFFFFFFFB
+#define   S_028B20_BUFFER_3_EN(x)                      (((x) & 0x1) << 3)
+#define   G_028B20_BUFFER_3_EN(x)                      (((x) >> 3) & 0x1)
+#define   C_028B20_BUFFER_3_EN                         0xFFFFFFF7
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX    0x028C20
+#define   S_028C20_S4_X(x)                             (((x) & 0xF) << 0)
+#define   G_028C20_S4_X(x)                             (((x) >> 0) & 0xF)
+#define   C_028C20_S4_X                                0xFFFFFFF0
+#define   S_028C20_S4_Y(x)                             (((x) & 0xF) << 4)
+#define   G_028C20_S4_Y(x)                             (((x) >> 4) & 0xF)
+#define   C_028C20_S4_Y                                0xFFFFFF0F
+#define   S_028C20_S5_X(x)                             (((x) & 0xF) << 8)
+#define   G_028C20_S5_X(x)                             (((x) >> 8) & 0xF)
+#define   C_028C20_S5_X                                0xFFFFF0FF
+#define   S_028C20_S5_Y(x)                             (((x) & 0xF) << 12)
+#define   G_028C20_S5_Y(x)                             (((x) >> 12) & 0xF)
+#define   C_028C20_S5_Y                                0xFFFF0FFF
+#define   S_028C20_S6_X(x)                             (((x) & 0xF) << 16)
+#define   G_028C20_S6_X(x)                             (((x) >> 16) & 0xF)
+#define   C_028C20_S6_X                                0xFFF0FFFF
+#define   S_028C20_S6_Y(x)                             (((x) & 0xF) << 20)
+#define   G_028C20_S6_Y(x)                             (((x) >> 20) & 0xF)
+#define   C_028C20_S6_Y                                0xFF0FFFFF
+#define   S_028C20_S7_X(x)                             (((x) & 0xF) << 24)
+#define   G_028C20_S7_X(x)                             (((x) >> 24) & 0xF)
+#define   C_028C20_S7_X                                0xF0FFFFFF
+#define   S_028C20_S7_Y(x)                             (((x) & 0xF) << 28)
+#define   G_028C20_S7_Y(x)                             (((x) >> 28) & 0xF)
+#define   C_028C20_S7_Y                                0x0FFFFFFF
+#define R_028C30_CB_CLRCMP_CONTROL                   0x028C30
+#define   S_028C30_CLRCMP_FCN_SRC(x)                   (((x) & 0x7) << 0)
+#define   G_028C30_CLRCMP_FCN_SRC(x)                   (((x) >> 0) & 0x7)
+#define   C_028C30_CLRCMP_FCN_SRC                      0xFFFFFFF8
+#define   S_028C30_CLRCMP_FCN_DST(x)                   (((x) & 0x7) << 8)
+#define   G_028C30_CLRCMP_FCN_DST(x)                   (((x) >> 8) & 0x7)
+#define   C_028C30_CLRCMP_FCN_DST                      0xFFFFF8FF
+#define   S_028C30_CLRCMP_FCN_SEL(x)                   (((x) & 0x3) << 24)
+#define   G_028C30_CLRCMP_FCN_SEL(x)                   (((x) >> 24) & 0x3)
+#define   C_028C30_CLRCMP_FCN_SEL                      0xFCFFFFFF
+#define R_028C34_CB_CLRCMP_SRC                       0x028C34
+#define   S_028C34_CLRCMP_SRC(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C34_CLRCMP_SRC(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C34_CLRCMP_SRC                          0x00000000
+#define R_028C38_CB_CLRCMP_DST                       0x028C38
+#define   S_028C38_CLRCMP_DST(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C38_CLRCMP_DST(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C38_CLRCMP_DST                          0x00000000
+#define R_028C3C_CB_CLRCMP_MSK                       0x028C3C
+#define   S_028C3C_CLRCMP_MSK(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C3C_CLRCMP_MSK(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C3C_CLRCMP_MSK                          0x00000000
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CR_DEST_BASE_ENA(x)                 (((x) & 0x1) << 15)
+#define   G_0085F0_CR_DEST_BASE_ENA(x)                 (((x) >> 15) & 0x1)
+#define   C_0085F0_CR_DEST_BASE_ENA                    0xFFFF7FFF
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+
+
+#define R_02812C_CB_CLEAR_ALPHA                      0x02812C
+#define   S_02812C_CLEAR_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_02812C_CLEAR_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02812C_CLEAR_ALPHA                         0x00000000
+#define R_028128_CB_CLEAR_BLUE                       0x028128
+#define   S_028128_CLEAR_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028128_CLEAR_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028128_CLEAR_BLUE                          0x00000000
+#define R_028124_CB_CLEAR_GREEN                      0x028124
+#define   S_028124_CLEAR_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028124_CLEAR_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028124_CLEAR_GREEN                         0x00000000
+#define R_028120_CB_CLEAR_RED                        0x028120
+#define   S_028120_CLEAR_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028120_CLEAR_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028120_CLEAR_RED                           0x00000000
+#define R_02842C_CB_FOG_BLUE                         0x02842C
+#define   S_02842C_FOG_BLUE(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_02842C_FOG_BLUE(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02842C_FOG_BLUE                            0x00000000
+#define R_028428_CB_FOG_GREEN                        0x028428
+#define   S_028428_FOG_GREEN(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028428_FOG_GREEN(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028428_FOG_GREEN                           0x00000000
+#define R_028424_CB_FOG_RED                          0x028424
+#define   S_028424_FOG_RED(x)                          (((x) & 0xFFFFFFFF) << 0)
+#define   G_028424_FOG_RED(x)                          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028424_FOG_RED                             0x00000000
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA         0x00A40C
+#define   S_00A40C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A40C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A40C_BORDER_ALPHA                        0x00000000
+#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE          0x00A408
+#define   S_00A408_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A408_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A408_BORDER_BLUE                         0x00000000
+#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN         0x00A404
+#define   S_00A404_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A404_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A404_BORDER_GREEN                        0x00000000
+#define R_00A400_TD_PS_SAMPLER0_BORDER_RED           0x00A400
+#define   S_00A400_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A400_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A400_BORDER_RED                          0x00000000
+#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA         0x00A60C
+#define   S_00A60C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A60C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A60C_BORDER_ALPHA                        0x00000000
+#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE          0x00A608
+#define   S_00A608_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A608_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A608_BORDER_BLUE                         0x00000000
+#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN         0x00A604
+#define   S_00A604_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A604_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A604_BORDER_GREEN                        0x00000000
+#define R_00A600_TD_VS_SAMPLER0_BORDER_RED           0x00A600
+#define   S_00A600_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A600_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A600_BORDER_RED                          0x00000000
+#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA         0x00A80C
+#define   S_00A80C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A80C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A80C_BORDER_ALPHA                        0x00000000
+#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE          0x00A808
+#define   S_00A808_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A808_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A808_BORDER_BLUE                         0x00000000
+#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN         0x00A804
+#define   S_00A804_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A804_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A804_BORDER_GREEN                        0x00000000
+#define R_00A800_TD_GS_SAMPLER0_BORDER_RED           0x00A800
+#define   S_00A800_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A800_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A800_BORDER_RED                          0x00000000
+#define R_030000_SQ_ALU_CONSTANT0_0                  0x030000
+#define   S_030000_X(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030000_X(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030000_X                                   0x00000000
+#define R_030004_SQ_ALU_CONSTANT1_0                  0x030004
+#define   S_030004_Y(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030004_Y(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030004_Y                                   0x00000000
+#define R_030008_SQ_ALU_CONSTANT2_0                  0x030008
+#define   S_030008_Z(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_Z(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_Z                                   0x00000000
+#define R_03000C_SQ_ALU_CONSTANT3_0                  0x03000C
+#define   S_03000C_W(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_W(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_W                                   0x00000000
+#define R_0287E4_VGT_DMA_BASE_HI                     0x0287E4
+#define R_0287E8_VGT_DMA_BASE                        0x0287E8
+#define R_028E20_PA_CL_UCP0_X                        0x028E20
+#define R_028E24_PA_CL_UCP0_Y                        0x028E24
+#define R_028E28_PA_CL_UCP0_Z                        0x028E28
+#define R_028E2C_PA_CL_UCP0_W                        0x028E2C
+#define R_028E30_PA_CL_UCP1_X                        0x028E30
+#define R_028E34_PA_CL_UCP1_Y                        0x028E34
+#define R_028E38_PA_CL_UCP1_Z                        0x028E38
+#define R_028E3C_PA_CL_UCP1_W                        0x028E3C
+#define R_028E40_PA_CL_UCP2_X                        0x028E40
+#define R_028E44_PA_CL_UCP2_Y                        0x028E44
+#define R_028E48_PA_CL_UCP2_Z                        0x028E48
+#define R_028E4C_PA_CL_UCP2_W                        0x028E4C
+#define R_028E50_PA_CL_UCP3_X                        0x028E50
+#define R_028E54_PA_CL_UCP3_Y                        0x028E54
+#define R_028E58_PA_CL_UCP3_Z                        0x028E58
+#define R_028E5C_PA_CL_UCP3_W                        0x028E5C
+#define R_028E60_PA_CL_UCP4_X                        0x028E60
+#define R_028E64_PA_CL_UCP4_Y                        0x028E64
+#define R_028E68_PA_CL_UCP4_Z                        0x028E68
+#define R_028E6C_PA_CL_UCP4_W                        0x028E6C
+#define R_028E70_PA_CL_UCP5_X                        0x028E70
+#define R_028E74_PA_CL_UCP5_Y                        0x028E74
+#define R_028E78_PA_CL_UCP5_Z                        0x028E78
+#define R_028E7C_PA_CL_UCP5_W                        0x028E7C
+#define R_038000_RESOURCE0_WORD0                     0x038000
+#define R_038004_RESOURCE0_WORD1                     0x038004
+#define R_038008_RESOURCE0_WORD2                     0x038008
+#define R_03800C_RESOURCE0_WORD3                     0x03800C
+#define R_038010_RESOURCE0_WORD4                     0x038010
+#define R_038014_RESOURCE0_WORD5                     0x038014
+#define R_038018_RESOURCE0_WORD6                     0x038018
 
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
diff --git a/src/gallium/targets/dri-r600/target.c b/src/gallium/targets/dri-r600/target.c
index a01f4ed49fd..eb268d5bc01 100644
--- a/src/gallium/targets/dri-r600/target.c
+++ b/src/gallium/targets/dri-r600/target.c
@@ -4,6 +4,7 @@
 #include "r600/drm/r600_drm_public.h"
 #include "r600/r600_public.h"
 
+#if 1
 static struct pipe_screen *
 create_screen(int fd)
 {
@@ -22,5 +23,27 @@ create_screen(int fd)
 
    return screen;
 }
+#else
+struct radeon *r600_new(int fd, unsigned device);
+struct pipe_screen *r600_screen_create2(struct radeon *radeon);
+static struct pipe_screen *
+create_screen(int fd)
+{
+   struct radeon *radeon;
+   struct pipe_screen *screen;
+
+   radeon = r600_drm_winsys_create(fd);
+   if (!radeon)
+      return NULL;
+
+   screen = r600_screen_create2(radeon);
+   if (!screen)
+      return NULL;
+
+   screen = debug_screen_wrap(screen);
+
+   return screen;
+}
+#endif
 
 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen)
diff --git a/src/gallium/winsys/r600/drm/Makefile b/src/gallium/winsys/r600/drm/Makefile
index c81a075f1e8..9d8dc8dc594 100644
--- a/src/gallium/winsys/r600/drm/Makefile
+++ b/src/gallium/winsys/r600/drm/Makefile
@@ -7,6 +7,8 @@ LIBNAME = r600winsys
 C_SOURCES = \
 	bof.c \
 	r600_state.c \
+	r600_state2.c \
+	r600.c \
 	radeon_ctx.c \
 	radeon_draw.c \
 	radeon_state.c \
diff --git a/src/gallium/winsys/r600/drm/r600.c b/src/gallium/winsys/r600/drm/r600.c
new file mode 100644
index 00000000000..af9b9187ab1
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "r600_priv.h"
+
+enum radeon_family r600_get_family(struct radeon *r600)
+{
+	return r600->family;
+}
+
+static int r600_get_device(struct radeon *r600)
+{
+	struct drm_radeon_info info;
+
+	r600->device = 0;
+	info.request = RADEON_INFO_DEVICE_ID;
+	info.value = (uintptr_t)&r600->device;
+	return drmCommandWriteRead(r600->fd, DRM_RADEON_INFO, &info, sizeof(struct drm_radeon_info));
+}
+
+struct radeon *r600_new(int fd, unsigned device)
+{
+	struct radeon *r600;
+	int r;
+
+	r600 = calloc(1, sizeof(*r600));
+	if (r600 == NULL) {
+		return NULL;
+	}
+	r600->fd = fd;
+	r600->device = device;
+	if (fd >= 0) {
+		r = r600_get_device(r600);
+		if (r) {
+			R600_ERR("Failed to get device id\n");
+			r600_delete(r600);
+			return NULL;
+		}
+	}
+	r600->family = radeon_family_from_device(r600->device);
+	if (r600->family == CHIP_UNKNOWN) {
+		R600_ERR("Unknown chipset 0x%04X\n", r600->device);
+		r600_delete(r600);
+		return NULL;
+	}
+	switch (r600->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+	default:
+		R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
+		break;
+	}
+	return r600;
+}
+
+void r600_delete(struct radeon *r600)
+{
+	if (r600 == NULL)
+		return;
+	drmClose(r600->fd);
+	free(r600);
+}
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
new file mode 100644
index 00000000000..7a9025ad3c2
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_PRIV_H
+#define R600_PRIV_H
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "r600.h"
+
+
+struct radeon {
+	int				fd;
+	int				refcount;
+	unsigned			device;
+	unsigned			family;
+};
+
+struct radeon *r600_new(int fd, unsigned device);
+void r600_delete(struct radeon *r600);
+
+struct r600_reg {
+	unsigned		need_bo;
+	unsigned		flush_flags;
+	unsigned		offset;
+};
+
+
+/* radeon_pciid.c */
+unsigned radeon_family_from_device(unsigned device);
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c
new file mode 100644
index 00000000000..f6fba0a8dc5
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_state2.c
@@ -0,0 +1,1055 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "r600.h"
+#include "r600d.h"
+#include "r600_priv.h"
+#include "radeon_drm.h"
+#include "bof.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include <pipebuffer/pb_bufmgr.h>
+
+struct radeon_ws_bo {
+	struct pipe_reference reference;
+	struct pb_buffer *pb;
+};
+
+struct radeon_bo {
+	struct pipe_reference		reference;
+	unsigned			handle;
+	unsigned			size;
+	unsigned			alignment;
+	unsigned			map_count;
+	void				*data;
+};
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
+int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
+
+unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo);
+
+static int r600_group_id_register_offset(unsigned offset)
+{
+	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+		return R600_GROUP_CONFIG;
+	}
+	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+		return R600_GROUP_CONTEXT;
+	}
+	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
+		return R600_GROUP_ALU_CONST;
+	}
+	if (offset >= R600_RESOURCE_OFFSET && offset < R600_RESOURCE_END) {
+		return R600_GROUP_RESOURCE;
+	}
+	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+		return R600_GROUP_SAMPLER;
+	}
+	if (offset >= R600_CTL_CONST_OFFSET && offset < R600_CTL_CONST_END) {
+		return R600_GROUP_CTL_CONST;
+	}
+	if (offset >= R600_LOOP_CONST_OFFSET && offset < R600_LOOP_CONST_END) {
+		return R600_GROUP_LOOP_CONST;
+	}
+	if (offset >= R600_BOOL_CONST_OFFSET && offset < R600_BOOL_CONST_END) {
+		return R600_GROUP_BOOL_CONST;
+	}
+	return -1;
+}
+
+static int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
+{
+	struct r600_group_block *block, *tmp;
+	struct r600_group *group;
+	int group_id, id;
+
+	for (unsigned i = 0, n = 0; i < nreg; i += n) {
+		u32 j, r;
+		/* find number of consecutive registers */
+		for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
+			if (r != reg[j].offset) {
+				break;
+			}
+		}
+
+		/* find into which group this block is */
+		group_id = r600_group_id_register_offset(reg[i].offset);
+		assert(group_id >= 0);
+		group = &ctx->groups[group_id];
+
+		/* allocate new block */
+		tmp = realloc(group->blocks, (group->nblocks + 1) * sizeof(struct r600_group_block));
+		if (tmp == NULL) {
+			return -ENOMEM;
+		}
+		group->blocks = tmp;
+		block = &group->blocks[group->nblocks++];
+		for (int j = 0; j < n; j++) {
+			group->offset_block_id[((reg[i].offset - group->start_offset) >> 2) + j] = group->nblocks - 1;
+		}
+
+		/* initialize block */
+		memset(block, 0, sizeof(struct r600_group_block));
+		block->start_offset = reg[i].offset;
+		block->pm4_ndwords = n;
+		block->nreg = n;
+		for (j = 0; j < n; j++) {
+			if (reg[i+j].need_bo) {
+				block->nbo++;
+				assert(block->nbo < R600_BLOCK_MAX_BO);
+				block->pm4_bo_index[j] = block->nbo;
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				block->reloc[block->nbo].bo_pm4_index[block->reloc[block->nbo].nreloc++] = block->pm4_ndwords - 1;
+			}
+		}
+		for (j = 0; j < n; j++) {
+			if (reg[i+j].flush_flags) {
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+				block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
+				block->pm4[block->pm4_ndwords++] = 0xFFFFFFFF;
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				block->pm4[block->pm4_ndwords++] = 0x0000000A;
+				block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+				block->pm4[block->pm4_ndwords++] = 0x00000000;
+				id = block->pm4_bo_index[j];
+				block->reloc[id].bo_pm4_index[block->reloc[id].nreloc++] = block->pm4_ndwords - 1;
+			}
+		}
+		/* check that we stay in limit */
+		assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
+	}
+	return 0;
+}
+
+static int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
+{
+	group->start_offset = start_offset;
+	group->end_offset = end_offset;
+	group->nblocks = 0;
+	group->blocks = NULL;
+	group->offset_block_id = calloc((end_offset - start_offset) >> 2, sizeof(unsigned));
+	if (group->offset_block_id == NULL)
+		return -ENOMEM;
+	return 0;
+}
+
+static void r600_group_fini(struct r600_group *group)
+{
+	free(group->offset_block_id);
+	free(group->blocks);
+}
+
+/* R600/R700 configuration */
+static const struct r600_reg r600_reg_list[] = {
+	{0, 0, R_008C00_SQ_CONFIG},
+	{0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1},
+	{0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2},
+	{0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT},
+	{0, 0, R_008C10_SQ_STACK_RESOURCE_MGMT_1},
+	{0, 0, R_008C14_SQ_STACK_RESOURCE_MGMT_2},
+	{0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ},
+	{0, 0, R_009508_TA_CNTL_AUX},
+	{0, 0, R_009714_VC_ENHANCE},
+	{0, 0, R_009830_DB_DEBUG},
+	{0, 0, R_009838_DB_WATERMARKS},
+	{0, 0, R_028350_SX_MISC},
+	{0, 0, R_0286C8_SPI_THREAD_GROUPING},
+	{0, 0, R_0288A8_SQ_ESGS_RING_ITEMSIZE},
+	{0, 0, R_0288AC_SQ_GSVS_RING_ITEMSIZE},
+	{0, 0, R_0288B0_SQ_ESTMP_RING_ITEMSIZE},
+	{0, 0, R_0288B4_SQ_GSTMP_RING_ITEMSIZE},
+	{0, 0, R_0288B8_SQ_VSTMP_RING_ITEMSIZE},
+	{0, 0, R_0288BC_SQ_PSTMP_RING_ITEMSIZE},
+	{0, 0, R_0288C0_SQ_FBUF_RING_ITEMSIZE},
+	{0, 0, R_0288C4_SQ_REDUC_RING_ITEMSIZE},
+	{0, 0, R_0288C8_SQ_GS_VERT_ITEMSIZE},
+	{0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL},
+	{0, 0, R_028A14_VGT_HOS_CNTL},
+	{0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL},
+	{0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL},
+	{0, 0, R_028A20_VGT_HOS_REUSE_DEPTH},
+	{0, 0, R_028A24_VGT_GROUP_PRIM_TYPE},
+	{0, 0, R_028A28_VGT_GROUP_FIRST_DECR},
+	{0, 0, R_028A2C_VGT_GROUP_DECR},
+	{0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL},
+	{0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL},
+	{0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL},
+	{0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL},
+	{0, 0, R_028A40_VGT_GS_MODE},
+	{0, 0, R_028A4C_PA_SC_MODE_CNTL},
+	{0, 0, R_028AB0_VGT_STRMOUT_EN},
+	{0, 0, R_028AB4_VGT_REUSE_OFF},
+	{0, 0, R_028AB8_VGT_VTX_CNT_EN},
+	{0, 0, R_028B20_VGT_STRMOUT_BUFFER_EN},
+	{0, 0, R_028028_DB_STENCIL_CLEAR},
+	{0, 0, R_02802C_DB_DEPTH_CLEAR},
+	{1, 0, R_028040_CB_COLOR0_BASE},
+	{0, 0, R_0280A0_CB_COLOR0_INFO},
+	{0, 0, R_028060_CB_COLOR0_SIZE},
+	{0, 0, R_028080_CB_COLOR0_VIEW},
+	{1, 0, R_0280E0_CB_COLOR0_FRAG},
+	{1, 0, R_0280C0_CB_COLOR0_TILE},
+	{0, 0, R_028100_CB_COLOR0_MASK},
+	{1, 0, R_028044_CB_COLOR1_BASE},
+	{0, 0, R_0280A4_CB_COLOR1_INFO},
+	{0, 0, R_028064_CB_COLOR1_SIZE},
+	{0, 0, R_028084_CB_COLOR1_VIEW},
+	{1, 0, R_0280E4_CB_COLOR1_FRAG},
+	{1, 0, R_0280C4_CB_COLOR1_TILE},
+	{0, 0, R_028104_CB_COLOR1_MASK},
+	{1, 0, R_028048_CB_COLOR2_BASE},
+	{0, 0, R_0280A8_CB_COLOR2_INFO},
+	{0, 0, R_028068_CB_COLOR2_SIZE},
+	{0, 0, R_028088_CB_COLOR2_VIEW},
+	{1, 0, R_0280E8_CB_COLOR2_FRAG},
+	{1, 0, R_0280C8_CB_COLOR2_TILE},
+	{0, 0, R_028108_CB_COLOR2_MASK},
+	{1, 0, R_02804C_CB_COLOR3_BASE},
+	{0, 0, R_0280AC_CB_COLOR3_INFO},
+	{0, 0, R_02806C_CB_COLOR3_SIZE},
+	{0, 0, R_02808C_CB_COLOR3_VIEW},
+	{1, 0, R_0280EC_CB_COLOR3_FRAG},
+	{1, 0, R_0280CC_CB_COLOR3_TILE},
+	{0, 0, R_02810C_CB_COLOR3_MASK},
+	{1, 0, R_028050_CB_COLOR4_BASE},
+	{0, 0, R_0280B0_CB_COLOR4_INFO},
+	{0, 0, R_028070_CB_COLOR4_SIZE},
+	{0, 0, R_028090_CB_COLOR4_VIEW},
+	{1, 0, R_0280F0_CB_COLOR4_FRAG},
+	{1, 0, R_0280D0_CB_COLOR4_TILE},
+	{0, 0, R_028110_CB_COLOR4_MASK},
+	{1, 0, R_028054_CB_COLOR5_BASE},
+	{0, 0, R_0280B4_CB_COLOR5_INFO},
+	{0, 0, R_028074_CB_COLOR5_SIZE},
+	{0, 0, R_028094_CB_COLOR5_VIEW},
+	{1, 0, R_0280F4_CB_COLOR5_FRAG},
+	{1, 0, R_0280D4_CB_COLOR5_TILE},
+	{0, 0, R_028114_CB_COLOR5_MASK},
+	{1, 0, R_028058_CB_COLOR6_BASE},
+	{0, 0, R_0280B8_CB_COLOR6_INFO},
+	{0, 0, R_028078_CB_COLOR6_SIZE},
+	{0, 0, R_028098_CB_COLOR6_VIEW},
+	{1, 0, R_0280F8_CB_COLOR6_FRAG},
+	{1, 0, R_0280D8_CB_COLOR6_TILE},
+	{0, 0, R_028118_CB_COLOR6_MASK},
+	{1, 0, R_02805C_CB_COLOR7_BASE},
+	{0, 0, R_0280BC_CB_COLOR7_INFO},
+	{0, 0, R_02807C_CB_COLOR7_SIZE},
+	{0, 0, R_02809C_CB_COLOR7_VIEW},
+	{1, 0, R_0280FC_CB_COLOR7_FRAG},
+	{1, 0, R_0280DC_CB_COLOR7_TILE},
+	{0, 0, R_02811C_CB_COLOR7_MASK},
+	{0, 0, R_028120_CB_CLEAR_RED},
+	{0, 0, R_028124_CB_CLEAR_GREEN},
+	{0, 0, R_028128_CB_CLEAR_BLUE},
+	{0, 0, R_02812C_CB_CLEAR_ALPHA},
+	{0, 0, R_02823C_CB_SHADER_MASK},
+	{0, 0, R_028238_CB_TARGET_MASK},
+	{0, 0, R_028410_SX_ALPHA_TEST_CONTROL},
+	{0, 0, R_028414_CB_BLEND_RED},
+	{0, 0, R_028418_CB_BLEND_GREEN},
+	{0, 0, R_02841C_CB_BLEND_BLUE},
+	{0, 0, R_028420_CB_BLEND_ALPHA},
+	{0, 0, R_028424_CB_FOG_RED},
+	{0, 0, R_028428_CB_FOG_GREEN},
+	{0, 0, R_02842C_CB_FOG_BLUE},
+	{0, 0, R_028430_DB_STENCILREFMASK},
+	{0, 0, R_028434_DB_STENCILREFMASK_BF},
+	{0, 0, R_028438_SX_ALPHA_REF},
+	{0, 0, R_0286DC_SPI_FOG_CNTL},
+	{0, 0, R_0286E0_SPI_FOG_FUNC_SCALE},
+	{0, 0, R_0286E4_SPI_FOG_FUNC_BIAS},
+	{0, 0, R_028780_CB_BLEND0_CONTROL},
+	{0, 0, R_028784_CB_BLEND1_CONTROL},
+	{0, 0, R_028788_CB_BLEND2_CONTROL},
+	{0, 0, R_02878C_CB_BLEND3_CONTROL},
+	{0, 0, R_028790_CB_BLEND4_CONTROL},
+	{0, 0, R_028794_CB_BLEND5_CONTROL},
+	{0, 0, R_028798_CB_BLEND6_CONTROL},
+	{0, 0, R_02879C_CB_BLEND7_CONTROL},
+	{0, 0, R_0287A0_CB_SHADER_CONTROL},
+	{0, 0, R_028800_DB_DEPTH_CONTROL},
+	{0, 0, R_028804_CB_BLEND_CONTROL},
+	{0, 0, R_028808_CB_COLOR_CONTROL},
+	{0, 0, R_02880C_DB_SHADER_CONTROL},
+	{0, 0, R_028C04_PA_SC_AA_CONFIG},
+	{0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX},
+	{0, 0, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX},
+	{0, 0, R_028C30_CB_CLRCMP_CONTROL},
+	{0, 0, R_028C34_CB_CLRCMP_SRC},
+	{0, 0, R_028C38_CB_CLRCMP_DST},
+	{0, 0, R_028C3C_CB_CLRCMP_MSK},
+	{0, 0, R_028C48_PA_SC_AA_MASK},
+	{0, 0, R_028D2C_DB_SRESULTS_COMPARE_STATE1},
+	{0, 0, R_028D44_DB_ALPHA_TO_MASK},
+	{1, 0, R_02800C_DB_DEPTH_BASE},
+	{0, 0, R_028000_DB_DEPTH_SIZE},
+	{0, 0, R_028004_DB_DEPTH_VIEW},
+	{0, 0, R_028010_DB_DEPTH_INFO},
+	{0, 0, R_028D0C_DB_RENDER_CONTROL},
+	{0, 0, R_028D10_DB_RENDER_OVERRIDE},
+	{0, 0, R_028D24_DB_HTILE_SURFACE},
+	{0, 0, R_028D30_DB_PRELOAD_CONTROL},
+	{0, 0, R_028D34_DB_PREFETCH_LIMIT},
+	{0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
+	{0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
+	{0, 0, R_028200_PA_SC_WINDOW_OFFSET},
+	{0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL},
+	{0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR},
+	{0, 0, R_02820C_PA_SC_CLIPRECT_RULE},
+	{0, 0, R_028210_PA_SC_CLIPRECT_0_TL},
+	{0, 0, R_028214_PA_SC_CLIPRECT_0_BR},
+	{0, 0, R_028218_PA_SC_CLIPRECT_1_TL},
+	{0, 0, R_02821C_PA_SC_CLIPRECT_1_BR},
+	{0, 0, R_028220_PA_SC_CLIPRECT_2_TL},
+	{0, 0, R_028224_PA_SC_CLIPRECT_2_BR},
+	{0, 0, R_028228_PA_SC_CLIPRECT_3_TL},
+	{0, 0, R_02822C_PA_SC_CLIPRECT_3_BR},
+	{0, 0, R_028230_PA_SC_EDGERULE},
+	{0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL},
+	{0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR},
+	{0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL},
+	{0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR},
+	{0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0},
+	{0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0},
+	{0, 0, R_02843C_PA_CL_VPORT_XSCALE_0},
+	{0, 0, R_028440_PA_CL_VPORT_XOFFSET_0},
+	{0, 0, R_028444_PA_CL_VPORT_YSCALE_0},
+	{0, 0, R_028448_PA_CL_VPORT_YOFFSET_0},
+	{0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0},
+	{0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0},
+	{0, 0, R_0286D4_SPI_INTERP_CONTROL_0},
+	{0, 0, R_028810_PA_CL_CLIP_CNTL},
+	{0, 0, R_028814_PA_SU_SC_MODE_CNTL},
+	{0, 0, R_028818_PA_CL_VTE_CNTL},
+	{0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
+	{0, 0, R_028820_PA_CL_NANINF_CNTL},
+	{0, 0, R_028A00_PA_SU_POINT_SIZE},
+	{0, 0, R_028A04_PA_SU_POINT_MINMAX},
+	{0, 0, R_028A08_PA_SU_LINE_CNTL},
+	{0, 0, R_028A0C_PA_SC_LINE_STIPPLE},
+	{0, 0, R_028A48_PA_SC_MPASS_PS_CNTL},
+	{0, 0, R_028C00_PA_SC_LINE_CNTL},
+	{0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ},
+	{0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ},
+	{0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ},
+	{0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ},
+	{0, 0, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL},
+	{0, 0, R_028DFC_PA_SU_POLY_OFFSET_CLAMP},
+	{0, 0, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE},
+	{0, 0, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET},
+	{0, 0, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE},
+	{0, 0, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET},
+	{0, 0, R_028E20_PA_CL_UCP0_X},
+	{0, 0, R_028E24_PA_CL_UCP0_Y},
+	{0, 0, R_028E28_PA_CL_UCP0_Z},
+	{0, 0, R_028E2C_PA_CL_UCP0_W},
+	{0, 0, R_028E30_PA_CL_UCP1_X},
+	{0, 0, R_028E34_PA_CL_UCP1_Y},
+	{0, 0, R_028E38_PA_CL_UCP1_Z},
+	{0, 0, R_028E3C_PA_CL_UCP1_W},
+	{0, 0, R_028E40_PA_CL_UCP2_X},
+	{0, 0, R_028E44_PA_CL_UCP2_Y},
+	{0, 0, R_028E48_PA_CL_UCP2_Z},
+	{0, 0, R_028E4C_PA_CL_UCP2_W},
+	{0, 0, R_028E50_PA_CL_UCP3_X},
+	{0, 0, R_028E54_PA_CL_UCP3_Y},
+	{0, 0, R_028E58_PA_CL_UCP3_Z},
+	{0, 0, R_028E5C_PA_CL_UCP3_W},
+	{0, 0, R_028E60_PA_CL_UCP4_X},
+	{0, 0, R_028E64_PA_CL_UCP4_Y},
+	{0, 0, R_028E68_PA_CL_UCP4_Z},
+	{0, 0, R_028E6C_PA_CL_UCP4_W},
+	{0, 0, R_028E70_PA_CL_UCP5_X},
+	{0, 0, R_028E74_PA_CL_UCP5_Y},
+	{0, 0, R_028E78_PA_CL_UCP5_Z},
+	{0, 0, R_028E7C_PA_CL_UCP5_W},
+	{0, 0, R_028380_SQ_VTX_SEMANTIC_0},
+	{0, 0, R_028384_SQ_VTX_SEMANTIC_1},
+	{0, 0, R_028388_SQ_VTX_SEMANTIC_2},
+	{0, 0, R_02838C_SQ_VTX_SEMANTIC_3},
+	{0, 0, R_028390_SQ_VTX_SEMANTIC_4},
+	{0, 0, R_028394_SQ_VTX_SEMANTIC_5},
+	{0, 0, R_028398_SQ_VTX_SEMANTIC_6},
+	{0, 0, R_02839C_SQ_VTX_SEMANTIC_7},
+	{0, 0, R_0283A0_SQ_VTX_SEMANTIC_8},
+	{0, 0, R_0283A4_SQ_VTX_SEMANTIC_9},
+	{0, 0, R_0283A8_SQ_VTX_SEMANTIC_10},
+	{0, 0, R_0283AC_SQ_VTX_SEMANTIC_11},
+	{0, 0, R_0283B0_SQ_VTX_SEMANTIC_12},
+	{0, 0, R_0283B4_SQ_VTX_SEMANTIC_13},
+	{0, 0, R_0283B8_SQ_VTX_SEMANTIC_14},
+	{0, 0, R_0283BC_SQ_VTX_SEMANTIC_15},
+	{0, 0, R_0283C0_SQ_VTX_SEMANTIC_16},
+	{0, 0, R_0283C4_SQ_VTX_SEMANTIC_17},
+	{0, 0, R_0283C8_SQ_VTX_SEMANTIC_18},
+	{0, 0, R_0283CC_SQ_VTX_SEMANTIC_19},
+	{0, 0, R_0283D0_SQ_VTX_SEMANTIC_20},
+	{0, 0, R_0283D4_SQ_VTX_SEMANTIC_21},
+	{0, 0, R_0283D8_SQ_VTX_SEMANTIC_22},
+	{0, 0, R_0283DC_SQ_VTX_SEMANTIC_23},
+	{0, 0, R_0283E0_SQ_VTX_SEMANTIC_24},
+	{0, 0, R_0283E4_SQ_VTX_SEMANTIC_25},
+	{0, 0, R_0283E8_SQ_VTX_SEMANTIC_26},
+	{0, 0, R_0283EC_SQ_VTX_SEMANTIC_27},
+	{0, 0, R_0283F0_SQ_VTX_SEMANTIC_28},
+	{0, 0, R_0283F4_SQ_VTX_SEMANTIC_29},
+	{0, 0, R_0283F8_SQ_VTX_SEMANTIC_30},
+	{0, 0, R_0283FC_SQ_VTX_SEMANTIC_31},
+	{0, 0, R_028614_SPI_VS_OUT_ID_0},
+	{0, 0, R_028618_SPI_VS_OUT_ID_1},
+	{0, 0, R_02861C_SPI_VS_OUT_ID_2},
+	{0, 0, R_028620_SPI_VS_OUT_ID_3},
+	{0, 0, R_028624_SPI_VS_OUT_ID_4},
+	{0, 0, R_028628_SPI_VS_OUT_ID_5},
+	{0, 0, R_02862C_SPI_VS_OUT_ID_6},
+	{0, 0, R_028630_SPI_VS_OUT_ID_7},
+	{0, 0, R_028634_SPI_VS_OUT_ID_8},
+	{0, 0, R_028638_SPI_VS_OUT_ID_9},
+	{0, 0, R_0286C4_SPI_VS_OUT_CONFIG},
+	{1, 0, R_028858_SQ_PGM_START_VS},
+	{0, S_0085F0_SH_ACTION_ENA(1), R_028868_SQ_PGM_RESOURCES_VS},
+	{1, 0, R_028894_SQ_PGM_START_FS},
+	{0, S_0085F0_SH_ACTION_ENA(1), R_0288A4_SQ_PGM_RESOURCES_FS},
+	{0, 0, R_0288D0_SQ_PGM_CF_OFFSET_VS},
+	{0, 0, R_0288DC_SQ_PGM_CF_OFFSET_FS},
+	{0, 0, R_028644_SPI_PS_INPUT_CNTL_0},
+	{0, 0, R_028648_SPI_PS_INPUT_CNTL_1},
+	{0, 0, R_02864C_SPI_PS_INPUT_CNTL_2},
+	{0, 0, R_028650_SPI_PS_INPUT_CNTL_3},
+	{0, 0, R_028654_SPI_PS_INPUT_CNTL_4},
+	{0, 0, R_028658_SPI_PS_INPUT_CNTL_5},
+	{0, 0, R_02865C_SPI_PS_INPUT_CNTL_6},
+	{0, 0, R_028660_SPI_PS_INPUT_CNTL_7},
+	{0, 0, R_028664_SPI_PS_INPUT_CNTL_8},
+	{0, 0, R_028668_SPI_PS_INPUT_CNTL_9},
+	{0, 0, R_02866C_SPI_PS_INPUT_CNTL_10},
+	{0, 0, R_028670_SPI_PS_INPUT_CNTL_11},
+	{0, 0, R_028674_SPI_PS_INPUT_CNTL_12},
+	{0, 0, R_028678_SPI_PS_INPUT_CNTL_13},
+	{0, 0, R_02867C_SPI_PS_INPUT_CNTL_14},
+	{0, 0, R_028680_SPI_PS_INPUT_CNTL_15},
+	{0, 0, R_028684_SPI_PS_INPUT_CNTL_16},
+	{0, 0, R_028688_SPI_PS_INPUT_CNTL_17},
+	{0, 0, R_02868C_SPI_PS_INPUT_CNTL_18},
+	{0, 0, R_028690_SPI_PS_INPUT_CNTL_19},
+	{0, 0, R_028694_SPI_PS_INPUT_CNTL_20},
+	{0, 0, R_028698_SPI_PS_INPUT_CNTL_21},
+	{0, 0, R_02869C_SPI_PS_INPUT_CNTL_22},
+	{0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23},
+	{0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24},
+	{0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25},
+	{0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26},
+	{0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27},
+	{0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28},
+	{0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29},
+	{0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30},
+	{0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31},
+	{0, 0, R_0286CC_SPI_PS_IN_CONTROL_0},
+	{0, 0, R_0286D0_SPI_PS_IN_CONTROL_1},
+	{0, 0, R_0286D8_SPI_INPUT_Z},
+	{1, S_0085F0_SH_ACTION_ENA(1), R_028840_SQ_PGM_START_PS},
+	{0, 0, R_028850_SQ_PGM_RESOURCES_PS},
+	{0, 0, R_028854_SQ_PGM_EXPORTS_PS},
+	{0, 0, R_0288CC_SQ_PGM_CF_OFFSET_PS},
+	{0, 0, R_008958_VGT_PRIMITIVE_TYPE},
+	{0, 0, R_028400_VGT_MAX_VTX_INDX},
+	{0, 0, R_028404_VGT_MIN_VTX_INDX},
+	{0, 0, R_028408_VGT_INDX_OFFSET},
+	{0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX},
+	{0, 0, R_028A84_VGT_PRIMITIVEID_EN},
+	{0, 0, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN},
+	{0, 0, R_028AA0_VGT_INSTANCE_STEP_RATE_0},
+	{0, 0, R_028AA4_VGT_INSTANCE_STEP_RATE_1},
+};
+
+/* SHADER CONSTANT R600/R700 */
+static int r600_state_constant_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_constant[] = {
+		{0, 0, R_030000_SQ_ALU_CONSTANT0_0},
+		{0, 0, R_030004_SQ_ALU_CONSTANT1_0},
+		{0, 0, R_030008_SQ_ALU_CONSTANT2_0},
+		{0, 0, R_03000C_SQ_ALU_CONSTANT3_0},
+	};
+	unsigned nreg = sizeof(r600_shader_constant)/sizeof(struct r600_reg);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_constant[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_constant, nreg);
+}
+
+/* SHADER RESOURCE R600/R700 */
+static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_resource[] = {
+		{0, 0, R_038000_RESOURCE0_WORD0},
+		{0, 0, R_038004_RESOURCE0_WORD1},
+		{1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_038008_RESOURCE0_WORD2},
+		{1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_03800C_RESOURCE0_WORD3},
+		{0, 0, R_038010_RESOURCE0_WORD4},
+		{0, 0, R_038014_RESOURCE0_WORD5},
+		{0, 0, R_038018_RESOURCE0_WORD6},
+	};
+	unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_resource[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_resource, nreg);
+}
+
+/* SHADER SAMPLER R600/R700 */
+static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_sampler[] = {
+		{0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0},
+		{0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0},
+		{0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0},
+	};
+	unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+}
+
+/* SHADER SAMPLER BORDER R600/R700 */
+static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
+{
+	struct r600_reg r600_shader_sampler_border[] = {
+		{0, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED},
+		{0, 0, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN},
+		{0, 0, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE},
+		{0, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA},
+	};
+	unsigned nreg = sizeof(r600_shader_sampler_border)/sizeof(struct r600_reg);
+
+	for (int i = 0; i < nreg; i++) {
+		r600_shader_sampler_border[i].offset += offset;
+	}
+	return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+}
+
+/* initialize */
+void r600_context_fini(struct r600_context *ctx)
+{
+	for (int i = 0; i < ctx->ngroups; i++) {
+		r600_group_fini(&ctx->groups[i]);
+	}
+	free(ctx->reloc);
+	free(ctx->pm4);
+	memset(ctx, 0, sizeof(struct r600_context));
+}
+
+int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
+{
+	int r;
+
+	memset(ctx, 0, sizeof(struct r600_context));
+	ctx->radeon = radeon;
+	/* initialize groups */
+	r = r600_group_init(&ctx->groups[R600_GROUP_CONFIG], R600_CONFIG_REG_OFFSET, R600_CONFIG_REG_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_CTL_CONST], R600_CTL_CONST_OFFSET, R600_CTL_CONST_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_LOOP_CONST], R600_LOOP_CONST_OFFSET, R600_LOOP_CONST_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_BOOL_CONST], R600_BOOL_CONST_OFFSET, R600_BOOL_CONST_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_SAMPLER], R600_SAMPLER_OFFSET, R600_SAMPLER_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_RESOURCE], R600_RESOURCE_OFFSET, R600_RESOURCE_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_ALU_CONST], R600_ALU_CONST_OFFSET, R600_ALU_CONST_END);
+	if (r) {
+		goto out_err;
+	}
+	r = r600_group_init(&ctx->groups[R600_GROUP_CONTEXT], R600_CONTEXT_REG_OFFSET, R600_CONTEXT_REG_END);
+	if (r) {
+		goto out_err;
+	}
+	ctx->ngroups = R600_NGROUPS;
+
+	/* add blocks */
+	r = r600_context_add_block(ctx, r600_reg_list, sizeof(r600_reg_list)/sizeof(struct r600_reg));
+	if (r)
+		goto out_err;
+
+	/* PS SAMPLER BORDER */
+	for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
+		r = r600_state_sampler_border_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+
+	/* VS SAMPLER BORDER */
+	for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
+		r = r600_state_sampler_border_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS SAMPLER */
+	for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS SAMPLER */
+	for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
+		r = r600_state_sampler_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS RESOURCE */
+	for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
+		r = r600_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS RESOURCE */
+	for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
+		r = r600_state_resource_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* PS CONSTANT */
+	for (int j = 0, offset = 0; j < 256; j++, offset += 0x10) {
+		r = r600_state_constant_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+	/* VS CONSTANT */
+	for (int j = 0, offset = 0x1000; j < 256; j++, offset += 0x10) {
+		r = r600_state_constant_init(ctx, offset);
+		if (r)
+			goto out_err;
+	}
+
+	/* allocate cs variables */
+	ctx->nreloc = RADEON_CTX_MAX_PM4;
+	ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
+	if (ctx->reloc == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+	if (ctx->bo == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
+	ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
+	if (ctx->pm4 == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	return 0;
+out_err:
+	r600_context_fini(ctx);
+	return r;
+}
+
+static void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_ws_bo *bo)
+{
+	int i, reloc_id;
+	unsigned handle = radeon_ws_bo_get_handle(bo);
+
+	assert(bo != NULL);
+	for (i = 0, reloc_id = -1; i < ctx->creloc; i++) {
+		if (ctx->reloc[i].handle == handle) {
+			reloc_id = i * sizeof(struct r600_reloc) / 4;
+			/* set PKT3 to point to proper reloc */
+			*pm4 = reloc_id;
+		}
+	}
+	if (reloc_id == -1) {
+		/* add new relocation */
+		if (ctx->creloc >= ctx->nreloc) {
+			r600_context_flush(ctx);
+		}
+		reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
+		ctx->reloc[ctx->creloc].handle = handle;
+		ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT;
+		ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT;
+		ctx->reloc[ctx->creloc].flags = 0;
+		radeon_ws_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
+		ctx->creloc++;
+		/* set PKT3 to point to proper reloc */
+		*pm4 = reloc_id;
+	}
+}
+
+void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
+{
+	struct r600_group *group;
+	struct r600_group_block *block;
+
+	for (int i = 0; i < state->nregs; i++) {
+		unsigned id;
+		group = &ctx->groups[state->regs[i].group_id];
+		id = group->offset_block_id[(state->regs[i].offset - group->start_offset) >> 2];
+		block = &group->blocks[id];
+		id = (state->regs[i].offset - block->start_offset) >> 2;
+		block->pm4[id] &= ~state->regs[i].mask;
+		block->pm4[id] |= state->regs[i].value;
+		if (block->pm4_bo_index[id]) {
+			/* find relocation */
+			id = block->pm4_bo_index[id];
+			radeon_ws_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
+			for (int j = 0; j < block->reloc[id].nreloc; j++) {
+				r600_context_bo_reloc(ctx, &block->pm4[block->reloc[id].bo_pm4_index[j]],
+							block->reloc[id].bo);
+			}
+		}
+		block->status |= R600_BLOCK_STATUS_ENABLED;
+		block->status |= R600_BLOCK_STATUS_DIRTY;
+		ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+	}
+}
+
+static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_group_block *block;
+	unsigned id;
+
+	offset -= ctx->groups[R600_GROUP_RESOURCE].start_offset;
+	id = ctx->groups[R600_GROUP_RESOURCE].offset_block_id[offset >> 2];
+	block = &ctx->groups[R600_GROUP_RESOURCE].blocks[id];
+	block->pm4[0] = state->regs[0].value;
+	block->pm4[1] = state->regs[1].value;
+	block->pm4[2] = state->regs[2].value;
+	block->pm4[3] = state->regs[3].value;
+	block->pm4[4] = state->regs[4].value;
+	block->pm4[5] = state->regs[5].value;
+	block->pm4[6] = state->regs[6].value;
+	radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, block->reloc[1].bo);
+	radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, block->reloc[2].bo);
+	if (state->regs[0].bo) {
+		/* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+		 * we have single case btw VERTEX & TEXTURE resource
+		 */
+		radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+		radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+	} else {
+		/* TEXTURE RESOURCE */
+		radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+		radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+	}
+	r600_context_bo_reloc(ctx, &block->pm4[block->reloc[1].bo_pm4_index[0]], block->reloc[1].bo);
+	r600_context_bo_reloc(ctx, &block->pm4[block->reloc[2].bo_pm4_index[0]], block->reloc[2].bo);
+	block->status |= R600_BLOCK_STATUS_ENABLED;
+	block->status |= R600_BLOCK_STATUS_DIRTY;
+	ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
+
+	r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+	unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
+
+	r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_group_block *block;
+	unsigned id;
+
+	offset -= ctx->groups[R600_GROUP_SAMPLER].start_offset;
+	id = ctx->groups[R600_GROUP_SAMPLER].offset_block_id[offset >> 2];
+	block = &ctx->groups[R600_GROUP_SAMPLER].blocks[id];
+	block->pm4[0] = state->regs[0].value;
+	block->pm4[1] = state->regs[1].value;
+	block->pm4[2] = state->regs[2].value;
+	block->status |= R600_BLOCK_STATUS_ENABLED;
+	block->status |= R600_BLOCK_STATUS_DIRTY;
+	ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+	struct r600_group_block *block;
+	unsigned id;
+
+	offset -= ctx->groups[R600_GROUP_CONFIG].start_offset;
+	id = ctx->groups[R600_GROUP_CONFIG].offset_block_id[offset >> 2];
+	block = &ctx->groups[R600_GROUP_CONFIG].blocks[id];
+	block->pm4[0] = state->regs[3].value;
+	block->pm4[1] = state->regs[4].value;
+	block->pm4[2] = state->regs[5].value;
+	block->pm4[3] = state->regs[6].value;
+	block->status |= R600_BLOCK_STATUS_ENABLED;
+	block->status |= R600_BLOCK_STATUS_DIRTY;
+	ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C000 + id * 0xc;
+	r600_context_pipe_state_set_sampler(ctx, state, offset);
+	if (state->nregs > 3) {
+		offset = 0x0000A400 + id * 0x10;
+		r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+	}
+}
+
+void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+	unsigned offset;
+
+	offset = 0x0003C0D8 + id * 0xc;
+	r600_context_pipe_state_set_sampler(ctx, state, offset);
+	if (state->nregs > 3) {
+		offset = 0x0000A600 + id * 0x10;
+		r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+	}
+}
+
+static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
+{
+	for (int i = 0; i < group->nblocks; i++) {
+		struct r600_group_block *block = &group->blocks[i];
+		if (block->status & R600_BLOCK_STATUS_DIRTY) {
+			ctx->pm4[ctx->pm4_cdwords++] = PKT3(opcode, block->nreg);
+			ctx->pm4[ctx->pm4_cdwords++] = (block->start_offset - group->start_offset) >> 2;
+			memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
+			ctx->pm4_cdwords += block->pm4_ndwords;
+			block->status ^= R600_BLOCK_STATUS_DIRTY;
+		}
+	}
+}
+
+void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
+{
+	unsigned ndwords = 9;
+
+	if (draw->indices) {
+		ndwords = 13;
+		/* make sure there is enough relocation space before scheduling draw */
+		if (ctx->creloc >= (ctx->nreloc - 1)) {
+			r600_context_flush(ctx);
+		}
+	}
+	if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+		/* need to flush */
+		r600_context_flush(ctx);
+	}
+	/* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
+	if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
+		R600_ERR("context is too big to be scheduled\n");
+		return;
+	}
+	/* Ok we enough room to copy packet */
+	r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONFIG], PKT3_SET_CONFIG_REG);
+	r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG);
+	r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_ALU_CONST], PKT3_SET_ALU_CONST);
+	r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_SAMPLER], PKT3_SET_SAMPLER);
+	r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_RESOURCE], PKT3_SET_RESOURCE);
+	/* draw packet */
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+	if (draw->indices) {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset;
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+		ctx->pm4[ctx->pm4_cdwords++] = 0;
+		r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+	} else {
+		ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+		ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+	}
+	ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+	ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+}
+
+void r600_context_flush(struct r600_context *ctx)
+{
+	struct drm_radeon_cs drmib;
+	struct drm_radeon_cs_chunk chunks[2];
+	uint64_t chunk_array[2];
+	struct r600_group_block *block;
+	int r;
+
+	if (!ctx->pm4_cdwords)
+		return;
+
+#if 1
+	/* emit cs */
+	drmib.num_chunks = 2;
+	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
+	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
+	chunks[0].length_dw = ctx->pm4_cdwords;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
+	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
+	chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
+	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
+	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
+	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
+				sizeof(struct drm_radeon_cs));
+#endif
+	/* restart */
+	for (int i = 0; i < ctx->creloc; i++) {
+		radeon_ws_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
+	}
+	ctx->creloc = 0;
+	ctx->pm4_dirty_cdwords = 0;
+	ctx->pm4_cdwords = 0;
+	for (int i = 0; i < ctx->ngroups; i++) {
+		for (int j = 0; j < ctx->groups[i].nblocks; j++) {
+			/* mark enabled block as dirty */
+			block = &ctx->groups[i].blocks[j];
+			if (block->status & R600_BLOCK_STATUS_ENABLED) {
+				ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+				block->status |= R600_BLOCK_STATUS_DIRTY;
+				for (int k = 1; k <= block->nbo; k++) {
+					for (int l = 0; l < block->reloc[k].nreloc; l++) {
+						r600_context_bo_reloc(ctx,
+							&block->pm4[block->reloc[k].bo_pm4_index[l]],
+							block->reloc[k].bo);
+					}
+				}
+			}
+		}
+	}
+}
+
+void r600_context_dump_bof(struct r600_context *ctx, const char *file)
+{
+	bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
+	unsigned i;
+
+	root = device_id = bcs = blob = array = bo = size = handle = NULL;
+	root = bof_object();
+	if (root == NULL)
+		goto out_err;
+	device_id = bof_int32(ctx->radeon->device);
+	if (device_id == NULL)
+		return;
+	if (bof_object_set(root, "device_id", device_id))
+		goto out_err;
+	bof_decref(device_id);
+	device_id = NULL;
+	/* dump relocs */
+	blob = bof_blob(ctx->creloc * 16, ctx->reloc);
+	if (blob == NULL)
+		goto out_err;
+	if (bof_object_set(root, "reloc", blob))
+		goto out_err;
+	bof_decref(blob);
+	blob = NULL;
+	/* dump cs */
+	blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
+	if (blob == NULL)
+		goto out_err;
+	if (bof_object_set(root, "pm4", blob))
+		goto out_err;
+	bof_decref(blob);
+	blob = NULL;
+	/* dump bo */
+	array = bof_array();
+	if (array == NULL)
+		goto out_err;
+	for (i = 0; i < ctx->creloc; i++) {
+		struct radeon_bo *rbo = radeon_bo_pb_get_bo(ctx->bo[i]->pb);
+		bo = bof_object();
+		if (bo == NULL)
+			goto out_err;
+		size = bof_int32(rbo->size);
+		if (size == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "size", size))
+			goto out_err;
+		bof_decref(size);
+		size = NULL;
+		handle = bof_int32(rbo->handle);
+		if (handle == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "handle", handle))
+			goto out_err;
+		bof_decref(handle);
+		handle = NULL;
+		radeon_bo_map(ctx->radeon, rbo);
+		blob = bof_blob(rbo->size, rbo->data);
+		radeon_bo_unmap(ctx->radeon, rbo);
+		if (blob == NULL)
+			goto out_err;
+		if (bof_object_set(bo, "data", blob))
+			goto out_err;
+		bof_decref(blob);
+		blob = NULL;
+		if (bof_array_append(array, bo))
+			goto out_err;
+		bof_decref(bo);
+		bo = NULL;
+	}
+	if (bof_object_set(root, "bo", array))
+		goto out_err;
+	bof_dump_file(root, file);
+out_err:
+	bof_decref(blob);
+	bof_decref(array);
+	bof_decref(bo);
+	bof_decref(size);
+	bof_decref(handle);
+	bof_decref(device_id);
+	bof_decref(root);
+}
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 05f31571f42..c5d5fe9ddfc 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -26,6 +26,15 @@
 #ifndef R600D_H
 #define R600D_H
 
+/* evergreen values */
+#define EG_RESOURCE_OFFSET                 0x00030000
+#define EG_RESOURCE_END                    0x00030400
+#define EG_LOOP_CONST_OFFSET               0x0003A200
+#define EG_LOOP_CONST_END                  0x0003A26C
+#define EG_BOOL_CONST_OFFSET               0x0003A500
+#define EG_BOOL_CONST_END                  0x0003A506
+
+
 #define R600_CONFIG_REG_OFFSET                 0X00008000
 #define R600_CONFIG_REG_END                    0X0000AC00
 #define R600_CONTEXT_REG_OFFSET                0X00028000
@@ -43,15 +52,6 @@
 #define R600_BOOL_CONST_OFFSET                 0X0003E380
 #define R600_BOOL_CONST_END                    0X00040000
 
-/* evergreen values */
-#define EG_RESOURCE_OFFSET                 0x00030000
-#define EG_RESOURCE_END                    0x00030400
-#define EG_LOOP_CONST_OFFSET               0x0003A200
-#define EG_LOOP_CONST_END                  0x0003A26C
-#define EG_BOOL_CONST_OFFSET               0x0003A500
-#define EG_BOOL_CONST_END                  0x0003A506
-
-
 #define PKT3_NOP                               0x10
 #define PKT3_INDIRECT_BUFFER_END               0x17
 #define PKT3_SET_PREDICATION                   0x20
@@ -939,6 +939,13 @@
 #define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
 #define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
 #define   C_028080_SLICE_MAX                           0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW                      0x028084
+#define R_028088_CB_COLOR2_VIEW                      0x028088
+#define R_02808C_CB_COLOR3_VIEW                      0x02808C
+#define R_028090_CB_COLOR4_VIEW                      0x028090
+#define R_028094_CB_COLOR5_VIEW                      0x028094
+#define R_028098_CB_COLOR6_VIEW                      0x028098
+#define R_02809C_CB_COLOR7_VIEW                      0x02809C
 #define R_028100_CB_COLOR0_MASK                      0x028100
 #define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
 #define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
@@ -946,6 +953,13 @@
 #define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
 #define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
 #define   C_028100_FMASK_TILE_MAX                      0x00000FFF
+#define R_028104_CB_COLOR1_MASK                      0x028104
+#define R_028108_CB_COLOR2_MASK                      0x028108
+#define R_02810C_CB_COLOR3_MASK                      0x02810C
+#define R_028110_CB_COLOR4_MASK                      0x028110
+#define R_028114_CB_COLOR5_MASK                      0x028114
+#define R_028118_CB_COLOR6_MASK                      0x028118
+#define R_02811C_CB_COLOR7_MASK                      0x02811C
 #define R_028040_CB_COLOR0_BASE                      0x028040
 #define   S_028040_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
 #define   G_028040_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
@@ -954,10 +968,24 @@
 #define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
 #define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
 #define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280E4_CB_COLOR1_FRAG                      0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG                      0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG                      0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG                      0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG                      0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG                      0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG                      0x0280FC
 #define R_0280C0_CB_COLOR0_TILE                      0x0280C0
 #define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
 #define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
 #define   C_0280C0_BASE_256B                           0x00000000
+#define R_0280C4_CB_COLOR1_TILE                      0x0280C4
+#define R_0280C8_CB_COLOR2_TILE                      0x0280C8
+#define R_0280CC_CB_COLOR3_TILE                      0x0280CC
+#define R_0280D0_CB_COLOR4_TILE                      0x0280D0
+#define R_0280D4_CB_COLOR5_TILE                      0x0280D4
+#define R_0280D8_CB_COLOR6_TILE                      0x0280D8
+#define R_0280DC_CB_COLOR7_TILE                      0x0280DC
 #define R_028808_CB_COLOR_CONTROL                    0x028808
 #define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
 #define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
@@ -2130,5 +2158,36 @@
 #define   C_03000C_W                                   0x00000000
 #define R_0287E4_VGT_DMA_BASE_HI                     0x0287E4
 #define R_0287E8_VGT_DMA_BASE                        0x0287E8
+#define R_028E20_PA_CL_UCP0_X                        0x028E20
+#define R_028E24_PA_CL_UCP0_Y                        0x028E24
+#define R_028E28_PA_CL_UCP0_Z                        0x028E28
+#define R_028E2C_PA_CL_UCP0_W                        0x028E2C
+#define R_028E30_PA_CL_UCP1_X                        0x028E30
+#define R_028E34_PA_CL_UCP1_Y                        0x028E34
+#define R_028E38_PA_CL_UCP1_Z                        0x028E38
+#define R_028E3C_PA_CL_UCP1_W                        0x028E3C
+#define R_028E40_PA_CL_UCP2_X                        0x028E40
+#define R_028E44_PA_CL_UCP2_Y                        0x028E44
+#define R_028E48_PA_CL_UCP2_Z                        0x028E48
+#define R_028E4C_PA_CL_UCP2_W                        0x028E4C
+#define R_028E50_PA_CL_UCP3_X                        0x028E50
+#define R_028E54_PA_CL_UCP3_Y                        0x028E54
+#define R_028E58_PA_CL_UCP3_Z                        0x028E58
+#define R_028E5C_PA_CL_UCP3_W                        0x028E5C
+#define R_028E60_PA_CL_UCP4_X                        0x028E60
+#define R_028E64_PA_CL_UCP4_Y                        0x028E64
+#define R_028E68_PA_CL_UCP4_Z                        0x028E68
+#define R_028E6C_PA_CL_UCP4_W                        0x028E6C
+#define R_028E70_PA_CL_UCP5_X                        0x028E70
+#define R_028E74_PA_CL_UCP5_Y                        0x028E74
+#define R_028E78_PA_CL_UCP5_Z                        0x028E78
+#define R_028E7C_PA_CL_UCP5_W                        0x028E7C
+#define R_038000_RESOURCE0_WORD0                     0x038000
+#define R_038004_RESOURCE0_WORD1                     0x038004
+#define R_038008_RESOURCE0_WORD2                     0x038008
+#define R_03800C_RESOURCE0_WORD3                     0x03800C
+#define R_038010_RESOURCE0_WORD4                     0x038010
+#define R_038014_RESOURCE0_WORD5                     0x038014
+#define R_038018_RESOURCE0_WORD6                     0x038018
 
 #endif
-- 
cgit v1.2.3


From 3672bc14afe14334046589c869eb9ee7f5cfd137 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 24 Sep 2010 10:37:41 -0400
Subject: r600g: fix typo in evergreen define (resource are in
 [0x30000;0x34000] range)

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/winsys/r600/drm/r600d.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index c5d5fe9ddfc..3c60e5c11a7 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -28,7 +28,7 @@
 
 /* evergreen values */
 #define EG_RESOURCE_OFFSET                 0x00030000
-#define EG_RESOURCE_END                    0x00030400
+#define EG_RESOURCE_END                    0x00034000
 #define EG_LOOP_CONST_OFFSET               0x0003A200
 #define EG_LOOP_CONST_END                  0x0003A26C
 #define EG_BOOL_CONST_OFFSET               0x0003A500
-- 
cgit v1.2.3


From a852615946b98de2d832d4907f09649803577db7 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sun, 26 Sep 2010 12:06:46 -0400
Subject: r600g: disable early cull optimization when occlusion query running

When occlusion query are running we want to have accurate
fragment count thus disable any early culling optimization
GPU has.

Based on work from Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600.h               |  1 +
 src/gallium/winsys/r600/drm/evergreen_state.c | 13 +++++++++++++
 src/gallium/winsys/r600/drm/r600_priv.h       | 21 +++++++++++++++++++++
 src/gallium/winsys/r600/drm/r600_state2.c     | 16 ++++++++++++++++
 src/gallium/winsys/r600/drm/r600d.h           | 10 ++++++++++
 5 files changed, 61 insertions(+)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 65b029b065f..17d34409dc4 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -246,6 +246,7 @@ struct r600_context {
 	struct radeon_bo	**bo;
 	u32			*pm4;
 	struct list_head	query_list;
+	unsigned		num_query_running;
 };
 
 struct r600_draw {
diff --git a/src/gallium/winsys/r600/drm/evergreen_state.c b/src/gallium/winsys/r600/drm/evergreen_state.c
index f2038638d6b..860c836e858 100644
--- a/src/gallium/winsys/r600/drm/evergreen_state.c
+++ b/src/gallium/winsys/r600/drm/evergreen_state.c
@@ -75,6 +75,7 @@ static const struct r600_reg evergreen_reg_list[] = {
 	{0, 0, R_009100_SPI_CONFIG_CNTL},
 	{0, 0, R_00913C_SPI_CONFIG_CNTL_1},
 	{0, 0, R_028000_DB_RENDER_CONTROL},
+	{0, 0, R_028004_DB_COUNT_CONTROL},
 	{0, 0, R_028008_DB_DEPTH_VIEW},
 	{0, 0, R_02800C_DB_RENDER_OVERRIDE},
 	{0, 0, R_028010_DB_RENDER_OVERRIDE2},
@@ -589,6 +590,18 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
 		}
 	}
 
+	/* queries need some special values */
+	if (ctx->num_query_running) {
+		r600_context_reg(ctx, R600_GROUP_CONTEXT,
+				R_028004_DB_COUNT_CONTROL,
+				S_028004_PERFECT_ZPASS_COUNTS(1),
+				S_028004_PERFECT_ZPASS_COUNTS(1));
+		r600_context_reg(ctx, R600_GROUP_CONTEXT,
+				R_02800C_DB_RENDER_OVERRIDE,
+				S_02800C_NOOP_CULL_DISABLE(1),
+				S_02800C_NOOP_CULL_DISABLE(1));
+	}
+
 	if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
 		/* need to flush */
 		r600_context_flush(ctx);
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 92b2eb1dff1..25a65c6a10f 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -54,4 +54,25 @@ struct r600_reg {
 /* radeon_pciid.c */
 unsigned radeon_family_from_device(unsigned device);
 
+
+static void inline r600_context_reg(struct r600_context *ctx, unsigned group_id,
+					unsigned offset, unsigned value,
+					unsigned mask)
+{
+	struct r600_group *group = &ctx->groups[group_id];
+	struct r600_group_block *block;
+	unsigned id;
+
+	id = group->offset_block_id[(offset - group->start_offset) >> 2];
+	block = &group->blocks[id];
+	id = (offset - block->start_offset) >> 2;
+	block->pm4[id] &= ~mask;
+	block->pm4[id] |= value;
+	if (!(block->status & R600_BLOCK_STATUS_DIRTY)) {
+		ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+	}
+	block->status |= R600_BLOCK_STATUS_ENABLED;
+	block->status |= R600_BLOCK_STATUS_DIRTY;
+}
+
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c
index e1f32da91b0..d60c37fc90d 100644
--- a/src/gallium/winsys/r600/drm/r600_state2.c
+++ b/src/gallium/winsys/r600/drm/r600_state2.c
@@ -943,6 +943,20 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
 		}
 	}
 
+	/* queries need some special values */
+	if (ctx->num_query_running) {
+		if (ctx->radeon->family >= CHIP_RV770) {
+			r600_context_reg(ctx, R600_GROUP_CONTEXT,
+					R_028D0C_DB_RENDER_CONTROL,
+					S_028D0C_R700_PERFECT_ZPASS_COUNTS(1),
+					S_028D0C_R700_PERFECT_ZPASS_COUNTS(1));
+		}
+		r600_context_reg(ctx, R600_GROUP_CONTEXT,
+				R_028D10_DB_RENDER_OVERRIDE,
+				S_028D10_NOOP_CULL_DISABLE(1),
+				S_028D10_NOOP_CULL_DISABLE(1));
+	}
+
 	if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
 		/* need to flush */
 		r600_context_flush(ctx);
@@ -1181,6 +1195,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 
 	query->state |= R600_QUERY_STATE_STARTED;
 	query->state ^= R600_QUERY_STATE_ENDED;
+	ctx->num_query_running++;
 }
 
 void r600_query_end(struct r600_context *ctx, struct r600_query *query)
@@ -1197,6 +1212,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query)
 	query->num_results += 16;
 	query->state ^= R600_QUERY_STATE_STARTED;
 	query->state |= R600_QUERY_STATE_ENDED;
+	ctx->num_query_running--;
 }
 
 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 3c60e5c11a7..fcce2934d39 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -839,6 +839,16 @@
 #define R_028800_DB_DEPTH_CONTROL                    0x028800
 #define R_02880C_DB_SHADER_CONTROL                   0x02880C
 #define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define   S_028D0C_DEPTH_CLEAR_ENABLE(x)               (((x) & 0x1) << 0)
+#define   S_028D0C_STENCIL_CLEAR_ENABLE(x)             (((x) & 0x1) << 1)
+#define   S_028D0C_DEPTH_COPY_ENABLE(x)                (((x) & 0x1) << 2)
+#define   S_028D0C_STENCIL_COPY_ENABLE(x)              (((x) & 0x1) << 3)
+#define   S_028D0C_RESUMMARIZE_ENABLE(x)               (((x) & 0x1) << 4)
+#define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
+#define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028D0C_COPY_CENTROID(x)                    (((x) & 0x1) << 7)
+#define   S_028D0C_COPY_SAMPLE(x)                      (((x) & 0x1) << 8)
+#define   S_028D0C_R700_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
 #define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
 #define R_028D2C_DB_SRESULTS_COMPARE_STATE1          0x028D2C
 #define R_028D30_DB_PRELOAD_CONTROL                  0x028D30
-- 
cgit v1.2.3


From 153105cfbfd8d6ff30de144605016f6e4f2a1b9e Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 30 Sep 2010 10:43:26 -0400
Subject: r600g: use constant buffer instead of register for constant

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c         | 47 ++++++++++++---------------
 src/gallium/drivers/r600/r600d.h              |  5 +++
 src/gallium/winsys/r600/drm/r600_hw_context.c | 34 +++----------------
 src/gallium/winsys/r600/drm/r600d.h           |  5 +++
 4 files changed, 36 insertions(+), 55 deletions(-)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 23323f1ea2b..23c2e5964a4 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1148,41 +1148,35 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint
 					struct pipe_resource *buffer)
 {
 	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate;
-	struct pipe_transfer *transfer;
-	unsigned *nconst = NULL;
-	u32 *ptr, offset;
+	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
 
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
-		rstate = rctx->vs_const;
-		nconst = &rctx->vs_nconst;
-		offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
+		rctx->vs_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028980_ALU_CONST_CACHE_VS_0,
+					0, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 		break;
 	case PIPE_SHADER_FRAGMENT:
-		rstate = rctx->ps_const;
-		nconst = &rctx->ps_nconst;
-		offset = R_030000_SQ_ALU_CONSTANT0_0;
+		rctx->ps_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028940_ALU_CONST_CACHE_PS_0,
+					0, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
 		return;
 	}
-	if (buffer && buffer->width0 > 0) {
-		*nconst = buffer->width0 / 16;
-		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
-		if (ptr == NULL)
-			return;
-		for (int i = 0; i < *nconst; i++, offset += 0x10) {
-			rstate[i].nregs = 0;
-			r600_pipe_state_add_reg(&rstate[i], offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
-			r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
-		}
-		pipe_buffer_unmap(ctx, buffer, transfer);
-	}
 }
 
 static void *r600_create_shader_state(struct pipe_context *ctx,
@@ -1191,6 +1185,7 @@ static void *r600_create_shader_state(struct pipe_context *ctx,
 	struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
 	int r;
 
+	shader->shader.use_mem_constant = TRUE;
 	r =  r600_pipe_shader_create(ctx, shader, state->tokens);
 	if (r) {
 		return NULL;
@@ -1436,7 +1431,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
 		tmp |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	tmp |= S_008C00_DX9_CONSTS(1);
+	tmp |= S_008C00_DX9_CONSTS(0);
 	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
 	tmp |= S_008C00_PS_PRIO(ps_prio);
 	tmp |= S_008C00_VS_PRIO(vs_prio);
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 47ab1eb9650..169cda5295b 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -3484,6 +3484,11 @@
 #define R_038014_RESOURCE0_WORD5                     0x038014
 #define R_038018_RESOURCE0_WORD6                     0x038018
 
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
 #define SQ_TEX_INST_GET_GRADIENTS_V 0x8
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index d1cf9e93f8a..f363b698bc0 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -253,6 +253,10 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
@@ -479,23 +483,6 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0},
 };
 
-/* SHADER CONSTANT R600/R700 */
-static int r600_state_constant_init(struct r600_context *ctx, u32 offset)
-{
-	struct r600_reg r600_shader_constant[] = {
-		{PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, R_030000_SQ_ALU_CONSTANT0_0, 0, 0},
-		{PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, R_030004_SQ_ALU_CONSTANT1_0, 0, 0},
-		{PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, R_030008_SQ_ALU_CONSTANT2_0, 0, 0},
-		{PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, R_03000C_SQ_ALU_CONSTANT3_0, 0, 0},
-	};
-	unsigned nreg = sizeof(r600_shader_constant)/sizeof(struct r600_reg);
-
-	for (int i = 0; i < nreg; i++) {
-		r600_shader_constant[i].offset += offset;
-	}
-	return r600_context_add_block(ctx, r600_shader_constant, nreg);
-}
-
 /* SHADER RESOURCE R600/R700 */
 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
 {
@@ -578,6 +565,7 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 	int r;
 
 	memset(ctx, 0, sizeof(struct r600_context));
+	radeon->use_mem_constant = TRUE;
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 
@@ -640,18 +628,6 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 		if (r)
 			goto out_err;
 	}
-	/* PS CONSTANT */
-	for (int j = 0, offset = 0; j < 256; j++, offset += 0x10) {
-		r = r600_state_constant_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
-	/* VS CONSTANT */
-	for (int j = 0, offset = 0x1000; j < 256; j++, offset += 0x10) {
-		r = r600_state_constant_init(ctx, offset);
-		if (r)
-			goto out_err;
-	}
 
 	/* setup block table */
 	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index fcce2934d39..5c08c5a04d1 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -2200,4 +2200,9 @@
 #define R_038014_RESOURCE0_WORD5                     0x038014
 #define R_038018_RESOURCE0_WORD6                     0x038018
 
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+
 #endif
-- 
cgit v1.2.3


From 05d1d86907b12011fdb80e147ae68b4cd207f789 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 1 Oct 2010 09:43:14 +1000
Subject: r600g: add winsys support for CTL constants.

These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.
---
 src/gallium/drivers/r600/evergreen_state.c         |  2 ++
 src/gallium/drivers/r600/evergreend.h              |  6 ++++++
 src/gallium/drivers/r600/r600_state.c              |  2 ++
 src/gallium/drivers/r600/r600d.h                   |  3 +++
 src/gallium/winsys/r600/drm/evergreen_hw_context.c | 10 ++++++++++
 src/gallium/winsys/r600/drm/r600_hw_context.c      |  9 +++++++++
 src/gallium/winsys/r600/drm/r600d.h                |  3 +++
 7 files changed, 35 insertions(+)

(limited to 'src/gallium/winsys/r600/drm/r600d.h')

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 5775b04cc7a..21d3394ca60 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1450,6 +1450,8 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
 
 	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 		float offset_units = rctx->rasterizer->offset_units;
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 54b26f6fb69..ce2b667868b 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -40,6 +40,9 @@
 #define EVERGREEN_SAMPLER_OFFSET                    0X0003C000
 #define EVERGREEN_SAMPLER_END                       0X0003CFF0
 
+#define EVERGREEN_CTL_CONST_OFFSET                  0x0003CFF0
+#define EVERGREEN_CTL_CONST_END                     0x0003E200
+
 #define EVENT_TYPE_ZPASS_DONE                  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 
@@ -1890,4 +1893,7 @@
 #define R_008970_VGT_NUM_INDICES                     0x008970
 #define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                    0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC                  0x03CFF4
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 83eedd2040f..c86bad7ff55 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -126,6 +126,8 @@ static void r600_draw_common(struct r600_drawl *draw)
 	r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
 	/* build late state */
 	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 		float offset_units = rctx->rasterizer->offset_units;
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 169cda5295b..02e3734fcc8 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -3489,6 +3489,9 @@
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
 #define SQ_TEX_INST_GET_GRADIENTS_V 0x8
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index a92c32e7df9..225027b8a3e 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -61,6 +61,11 @@ static const struct r600_reg evergreen_config_reg_list[] = {
 	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0},
 };
 
+static const struct r600_reg evergreen_ctl_const_list[] = {
+	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg evergreen_context_reg_list[] = {
 	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0},
 	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0},
@@ -518,6 +523,11 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 				   Elements(evergreen_context_reg_list));
 	if (r)
 		goto out_err;
+	r = r600_context_add_block(ctx, evergreen_ctl_const_list,
+				   Elements(evergreen_ctl_const_list));
+	if (r)
+		goto out_err;
+
 
 	/* PS SAMPLER */
 	for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 53783e8f507..88a86d2cf28 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -134,6 +134,11 @@ static const struct r600_reg r600_config_reg_list[] = {
 	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0},
 };
 
+static const struct r600_reg r600_ctl_const_list[] = {
+	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg r600_context_reg_list[] = {
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0},
 	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0},
@@ -591,6 +596,10 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 				   Elements(r600_context_reg_list));
 	if (r)
 		goto out_err;
+	r = r600_context_add_block(ctx, r600_ctl_const_list,
+				   Elements(r600_ctl_const_list));
+	if (r)
+		goto out_err;
 
 	/* PS SAMPLER BORDER */
 	for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 5c08c5a04d1..ccc9ffaf8e3 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -2205,4 +2205,7 @@
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #endif
-- 
cgit v1.2.3