From fd0a7a382f2accea67396584826f5f8e40239ef3 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Thu, 26 May 2016 14:09:43 +0200 Subject: radeonsi: Add barrier before writing the tess factors. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The factors may be stored to LDs by another invocation than the invocation for vertex 0. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/gallium/drivers') diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 166b2e8a415..5e5bf68df5f 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -144,6 +144,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, struct si_shader *shader, LLVMTargetMachineRef tm); +static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data); + /* Ideally pass the sample mask input to the PS epilog as v13, which * is its usual location, so that the shader doesn't have to add v_mov. */ @@ -2534,6 +2538,8 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base, unsigned stride, outer_comps, inner_comps, i; struct lp_build_if_state if_ctx, inner_if_ctx; + si_llvm_emit_barrier(NULL, bld_base, NULL); + /* Do this only for invocation 0, because the tess levels are per-patch, * not per-vertex. * -- cgit v1.2.3