From 3dc39d0bca0f06454cb5cddf7571facb7671767a Mon Sep 17 00:00:00 2001 From: Roy Spliet Date: Fri, 6 Feb 2015 22:46:55 +0100 Subject: nv50/ir: Add emit support for MAD IMM format But don't enable generation of it in the opProperties, because we can't guarantee the SDST==SRC2 constraint until after register assignment. We'll add a post-RA folding pass to utilise this. Signed-off-by: Roy Spliet Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/gallium/drivers') diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp index 23e4babfed0..b1e740954f5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp @@ -939,6 +939,14 @@ CodeEmitterNV50::emitFMAD(const Instruction *i) code[0] = 0xe0000000; + if (i->src(1).getFile() == FILE_IMMEDIATE) { + code[1] = 0; + emitForm_IMM(i); + code[0] |= neg_mul << 15; + code[0] |= neg_add << 22; + if (i->saturate) + code[0] |= 1 << 8; + } else if (i->encSize == 4) { emitForm_MUL(i); code[0] |= neg_mul << 15; -- cgit v1.2.3