From 01a57c11cb7fe85196b9cb4b5a1555e6eb239297 Mon Sep 17 00:00:00 2001 From: Tim Rowley <timothy.o.rowley@intel.com> Date: Sun, 10 Dec 2017 23:54:30 -0600 Subject: swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex components Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com> --- src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/gallium/drivers/swr/rasterizer/codegen') diff --git a/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py b/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py index ac8b3badf6d..8bbf36d9b83 100644 --- a/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py +++ b/src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py @@ -46,6 +46,7 @@ intrinsics = [ ['VGATHERPS', 'x86_avx2_gather_d_ps_256', ['src', 'pBase', 'indices', 'mask', 'scale']], ['VGATHERPS_16', 'x86_avx512_gather_dps_512', ['src', 'pBase', 'indices', 'mask', 'scale']], ['VGATHERDD', 'x86_avx2_gather_d_d_256', ['src', 'pBase', 'indices', 'mask', 'scale']], + ['VGATHERDD_16', 'x86_avx512_gather_dpi_512', ['src', 'pBase', 'indices', 'mask', 'scale']], ['VPSRLI', 'x86_avx2_psrli_d', ['src', 'imm']], ['VPSRLI_16', 'x86_avx512_psrli_d_512', ['src', 'imm']], ['VSQRTPS', 'x86_avx_sqrt_ps_256', ['a']], -- cgit v1.2.3