From ba2e7c68ce8d37ebd666614a47abb33502b38ce5 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sun, 23 Oct 2016 13:08:46 +0200 Subject: gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/cik_sdma.c | 40 ++++++++++++------------- src/gallium/drivers/radeonsi/si_descriptors.c | 4 +-- src/gallium/drivers/radeonsi/si_dma.c | 42 +++++++++++++-------------- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_state.c | 30 +++++++++---------- src/gallium/drivers/radeonsi/si_state.h | 6 ++-- 6 files changed, 62 insertions(+), 62 deletions(-) (limited to 'src/gallium/drivers/radeonsi') diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 500afb07c0b..38833666a8d 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -120,8 +120,8 @@ static unsigned encode_tile_info(struct si_context *sctx, bool set_bpp) { struct radeon_info *info = &sctx->screen->b.info; - unsigned tile_index = tex->surface.tiling_index[level]; - unsigned macro_tile_index = tex->surface.macro_tile_index; + unsigned tile_index = tex->surface.u.legacy.tiling_index[level]; + unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[tile_index]; unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index]; @@ -129,7 +129,7 @@ static unsigned encode_tile_info(struct si_context *sctx, (G_009910_ARRAY_MODE(tile_mode) << 3) | (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) | /* Non-depth modes don't have TILE_SPLIT set. */ - ((util_logbase2(tex->surface.tile_split >> 6)) << 11) | + ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) | (G_009990_BANK_WIDTH(macro_tile_mode) << 15) | (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) | (G_009990_NUM_BANKS(macro_tile_mode) << 21) | @@ -150,21 +150,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, struct r600_texture *rdst = (struct r600_texture*)dst; unsigned bpp = rdst->surface.bpe; uint64_t dst_address = rdst->resource.gpu_address + - rdst->surface.level[dst_level].offset; + rdst->surface.u.legacy.level[dst_level].offset; uint64_t src_address = rsrc->resource.gpu_address + - rsrc->surface.level[src_level].offset; - unsigned dst_mode = rdst->surface.level[dst_level].mode; - unsigned src_mode = rsrc->surface.level[src_level].mode; - unsigned dst_tile_index = rdst->surface.tiling_index[dst_level]; - unsigned src_tile_index = rsrc->surface.tiling_index[src_level]; + rsrc->surface.u.legacy.level[src_level].offset; + unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; + unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode; + unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level]; + unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level]; unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index]; unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index]; unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode); unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode); - unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x; - unsigned src_pitch = rsrc->surface.level[src_level].nblk_x; - uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp; - uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp; + unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x; + unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x; + uint64_t dst_slice_pitch = rdst->surface.u.legacy.level[dst_level].slice_size / bpp; + uint64_t src_slice_pitch = rsrc->surface.u.legacy.level[src_level].slice_size / bpp; unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0, dst_level, rdst->surface.blk_w); unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0, @@ -182,10 +182,10 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, assert(src_level <= src->last_level); assert(dst_level <= dst->last_level); - assert(rdst->surface.level[dst_level].offset + + assert(rdst->surface.u.legacy.level[dst_level].offset + dst_slice_pitch * bpp * (dstz + src_box->depth) <= rdst->resource.buf->size); - assert(rsrc->surface.level[src_level].offset + + assert(rsrc->surface.u.legacy.level[src_level].offset + src_slice_pitch * bpp * (srcz + src_box->depth) <= rsrc->resource.buf->size); @@ -350,14 +350,14 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, * starts reading from an address preceding linear_address!!! */ start_linear_address = - linear->surface.level[linear_level].offset + + linear->surface.u.legacy.level[linear_level].offset + bpp * (linear_z * linear_slice_pitch + linear_y * linear_pitch + linear_x); start_linear_address -= (int)(bpp * (tiled_x % granularity)); end_linear_address = - linear->surface.level[linear_level].offset + + linear->surface.u.legacy.level[linear_level].offset + bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch + (linear_y + copy_height - 1) * linear_pitch + (linear_x + copy_width)); @@ -379,7 +379,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, copy_width_aligned % xalign == 0 && tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING && /* check if everything fits into the bitfields */ - tiled->surface.tile_split <= 4096 && + tiled->surface.u.legacy.tile_split <= 4096 && pitch_tile_max < (1 << 11) && slice_tile_max < (1 << 22) && linear_pitch <= (1 << 14) && @@ -423,8 +423,8 @@ static bool cik_sdma_copy_texture(struct si_context *sctx, /* check if these fit into the bitfields */ src_address % 256 == 0 && dst_address % 256 == 0 && - rsrc->surface.tile_split <= 4096 && - rdst->surface.tile_split <= 4096 && + rsrc->surface.u.legacy.tile_split <= 4096 && + rdst->surface.u.legacy.tile_split <= 4096 && dstx % 8 == 0 && dsty % 8 == 0 && srcx % 8 == 0 && diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index d9c0408be14..9c7eb08d58a 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -377,7 +377,7 @@ static void si_set_buf_desc_address(struct r600_resource *buf, * \param state descriptor to update */ void si_set_mutable_tex_desc_fields(struct r600_texture *tex, - const struct radeon_surf_level *base_level_info, + const struct legacy_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, uint32_t *state) @@ -746,7 +746,7 @@ static void si_set_shader_image(struct si_context *ctx, view->u.tex.last_layer, width, height, depth, desc, NULL); - si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level], + si_set_mutable_tex_desc_fields(tex, &tex->surface.u.legacy.level[level], level, level, util_format_get_blockwidth(view->format), false, desc); diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 9dbee3af381..500247fccfd 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -135,14 +135,14 @@ static void si_dma_copy_tile(struct si_context *ctx, struct radeon_winsys_cs *cs = ctx->b.dma.cs; struct r600_texture *rsrc = (struct r600_texture*)src; struct r600_texture *rdst = (struct r600_texture*)dst; - unsigned dst_mode = rdst->surface.level[dst_level].mode; + unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode; bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; struct r600_texture *rlinear = detile ? rdst : rsrc; struct r600_texture *rtiled = detile ? rsrc : rdst; unsigned linear_lvl = detile ? dst_level : src_level; unsigned tiled_lvl = detile ? src_level : dst_level; struct radeon_info *info = &ctx->screen->b.info; - unsigned index = rtiled->surface.tiling_index[tiled_lvl]; + unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl]; unsigned tile_mode = info->si_tile_mode_array[index]; unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; unsigned ncopy, height, cheight, i; @@ -151,7 +151,7 @@ static void si_dma_copy_tile(struct si_context *ctx, uint64_t base, addr; unsigned pipe_config; - assert(dst_mode != rsrc->surface.level[src_level].mode); + assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode); sub_cmd = SI_DMA_COPY_TILED; lbpp = util_logbase2(bpp); @@ -167,23 +167,23 @@ static void si_dma_copy_tile(struct si_context *ctx, assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format)); array_mode = G_009910_ARRAY_MODE(tile_mode); - slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x * - rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1; + slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x * + rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal * to the linear height */ - height = rtiled->surface.level[tiled_lvl].nblk_y; - base = rtiled->surface.level[tiled_lvl].offset; - addr = rlinear->surface.level[linear_lvl].offset; - addr += rlinear->surface.level[linear_lvl].slice_size * linear_z; + height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y; + base = rtiled->surface.u.legacy.level[tiled_lvl].offset; + addr = rlinear->surface.u.legacy.level[linear_lvl].offset; + addr += rlinear->surface.u.legacy.level[linear_lvl].slice_size * linear_z; addr += linear_y * pitch + linear_x * bpp; bank_h = G_009910_BANK_HEIGHT(tile_mode); bank_w = G_009910_BANK_WIDTH(tile_mode); mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode); /* Non-depth modes don't have TILE_SPLIT set. */ - tile_split = util_logbase2(rtiled->surface.tile_split >> 6); + tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6); nbanks = G_009910_NUM_BANKS(tile_mode); base += rtiled->resource.gpu_address; addr += rlinear->resource.gpu_address; @@ -268,20 +268,20 @@ static void si_dma_copy(struct pipe_context *ctx, dst_y = util_format_get_nblocksy(src->format, dst_y); bpp = rdst->surface.bpe; - dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; - src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe; + dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; + src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; src_w = u_minify(rsrc->resource.b.b.width0, src_level); dst_w = u_minify(rdst->resource.b.b.width0, dst_level); - dst_mode = rdst->surface.level[dst_level].mode; - src_mode = rsrc->surface.level[src_level].mode; + dst_mode = rdst->surface.u.legacy.level[dst_level].mode; + src_mode = rsrc->surface.u.legacy.level[src_level].mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w || src_box->width != src_w || src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) || src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) || - rsrc->surface.level[src_level].nblk_y != - rdst->surface.level[dst_level].nblk_y) { + rsrc->surface.u.legacy.level[src_level].nblk_y != + rdst->surface.u.legacy.level[dst_level].nblk_y) { /* FIXME si can do partial blit */ goto fallback; } @@ -300,14 +300,14 @@ static void si_dma_copy(struct pipe_context *ctx, * dst_x/y == 0 * dst_pitch == src_pitch */ - src_offset= rsrc->surface.level[src_level].offset; - src_offset += rsrc->surface.level[src_level].slice_size * src_box->z; + src_offset= rsrc->surface.u.legacy.level[src_level].offset; + src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z; src_offset += src_y * src_pitch + src_x * bpp; - dst_offset = rdst->surface.level[dst_level].offset; - dst_offset += rdst->surface.level[dst_level].slice_size * dst_z; + dst_offset = rdst->surface.u.legacy.level[dst_level].offset; + dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z; dst_offset += dst_y * dst_pitch + dst_x * bpp; si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset, - rsrc->surface.level[src_level].slice_size); + rsrc->surface.u.legacy.level[src_level].slice_size); } else { si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z, src, src_level, src_x, src_y, src_box->z, diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 617ec2054c8..174baaa01d3 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -123,7 +123,7 @@ struct si_sampler_view { * [4..7] = buffer descriptor */ uint32_t state[8]; uint32_t fmask_state[8]; - const struct radeon_surf_level *base_level_info; + const struct legacy_surf_level *base_level_info; unsigned base_level; unsigned block_width; bool is_stencil_sampler; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 9d208f81c79..57882ab6538 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2204,7 +2204,7 @@ static void si_initialize_color_surface(struct si_context *sctx, /* This must be set for fast clear to work without FMASK. */ if (!rtex->fmask.size && sctx->b.chip_class == SI) { - unsigned bankh = util_logbase2(rtex->surface.bankh); + unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh); surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } @@ -2219,7 +2219,7 @@ static void si_init_depth_surface(struct si_context *sctx, { struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; unsigned level = surf->base.u.tex.level; - struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; + struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level]; unsigned format, stencil_format; uint32_t z_info, s_info; @@ -2239,9 +2239,9 @@ static void si_init_depth_surface(struct si_context *sctx, assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); surf->db_depth_base = (rtex->resource.gpu_address + - rtex->surface.level[level].offset) >> 8; + rtex->surface.u.legacy.level[level].offset) >> 8; surf->db_stencil_base = (rtex->resource.gpu_address + - rtex->surface.stencil_level[level].offset) >> 8; + rtex->surface.u.legacy.stencil_level[level].offset) >> 8; z_info = S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); @@ -2250,9 +2250,9 @@ static void si_init_depth_surface(struct si_context *sctx, if (sctx->b.chip_class >= CIK) { struct radeon_info *info = &sctx->screen->b.info; - unsigned index = rtex->surface.tiling_index[level]; - unsigned stencil_index = rtex->surface.stencil_tiling_index[level]; - unsigned macro_index = rtex->surface.macro_tile_index; + unsigned index = rtex->surface.u.legacy.tiling_index[level]; + unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level]; + unsigned macro_index = rtex->surface.u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[index]; unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; @@ -2506,7 +2506,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom /* Colorbuffers. */ for (i = 0; i < nr_cbufs; i++) { - const struct radeon_surf_level *level_info; + const struct legacy_surf_level *level_info; unsigned pitch_tile_max, slice_tile_max, tile_mode_index; unsigned cb_color_base, cb_color_fmask, cb_color_attrib; unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice; @@ -2522,7 +2522,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom } tex = (struct r600_texture *)cb->base.texture; - level_info = &tex->surface.level[cb->base.u.tex.level]; + level_info = &tex->surface.u.legacy.level[cb->base.u.tex.level]; radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, &tex->resource, RADEON_USAGE_READWRITE, tex->resource.b.b.nr_samples > 1 ? @@ -2599,7 +2599,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */ radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + tex->dcc_offset + - tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8); + tex->surface.u.legacy.level[cb->base.u.tex.level].dcc_offset) >> 8); } for (; i < 8 ; i++) if (sctx->framebuffer.dirty_cbufs & (1 << i)) @@ -3036,7 +3036,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx, unsigned height, depth, width; unsigned last_layer = state->u.tex.last_layer; enum pipe_format pipe_format; - const struct radeon_surf_level *surflevel; + const struct legacy_surf_level *surflevel; if (!view) return NULL; @@ -3120,7 +3120,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx, tmp = tmp->flushed_depth_texture; } - surflevel = tmp->surface.level; + surflevel = tmp->surface.u.legacy.level; if (tmp->db_compatible) { if (!view->is_stencil_sampler) @@ -3141,7 +3141,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx, case PIPE_FORMAT_S8X24_UINT: case PIPE_FORMAT_X32_S8X24_UINT: pipe_format = PIPE_FORMAT_S8_UINT; - surflevel = tmp->surface.stencil_level; + surflevel = tmp->surface.u.legacy.stencil_level; break; default:; } @@ -3785,7 +3785,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen, res->width0, res->height0, res->depth0, desc, NULL); - si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0, + si_set_mutable_tex_desc_fields(rtex, &rtex->surface.u.legacy.level[0], 0, 0, rtex->surface.blk_w, false, desc); /* Clear the base address and set the relative DCC offset. */ @@ -3798,7 +3798,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen, /* Dwords [10:..] contain the mipmap level offsets. */ for (i = 0; i <= res->last_level; i++) - md->metadata[10+i] = rtex->surface.level[i].offset >> 8; + md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8; md->size_metadata = (11 + res->last_level) * 4; } diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 88827a8919d..28411e3f454 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -283,7 +283,7 @@ struct si_buffer_resources { void si_ce_reinitialize_all_descriptors(struct si_context *sctx); void si_ce_enable_loads(struct radeon_winsys_cs *ib); void si_set_mutable_tex_desc_fields(struct r600_texture *tex, - const struct radeon_surf_level *base_level_info, + const struct legacy_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, uint32_t *state); @@ -366,9 +366,9 @@ static inline unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) { if (stencil) - return rtex->surface.stencil_tiling_index[level]; + return rtex->surface.u.legacy.stencil_tiling_index[level]; else - return rtex->surface.tiling_index[level]; + return rtex->surface.u.legacy.tiling_index[level]; } #endif -- cgit v1.2.3