From 2edb0606397d16fe88d7b488285df379aaae5893 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sat, 26 Sep 2015 23:18:55 +0200 Subject: gallium/radeon: tell the winsys the exact resource binding types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the priority flags and expand them. This information will be used for debugging. Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/cik_sdma.c | 8 +++--- src/gallium/drivers/radeonsi/si_compute.c | 8 +++--- src/gallium/drivers/radeonsi/si_cp_dma.c | 6 ++-- src/gallium/drivers/radeonsi/si_descriptors.c | 37 +++++++++---------------- src/gallium/drivers/radeonsi/si_dma.c | 8 +++--- src/gallium/drivers/radeonsi/si_pm4.c | 3 +- src/gallium/drivers/radeonsi/si_state.c | 6 ++-- src/gallium/drivers/radeonsi/si_state_draw.c | 10 +++---- src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++++---- 9 files changed, 44 insertions(+), 54 deletions(-) (limited to 'src/gallium/drivers/radeonsi') diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 8b0ce9f1bb8..691d379bccd 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -62,9 +62,9 @@ static void cik_sdma_do_copy_buffer(struct si_context *ctx, r600_need_dma_space(&ctx->b, ncopy * 7); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ, - RADEON_PRIO_MIN); + RADEON_PRIO_SDMA_BUFFER); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE, - RADEON_PRIO_MIN); + RADEON_PRIO_SDMA_BUFFER); for (i = 0; i < ncopy; i++) { csize = size < CIK_SDMA_COPY_MAX_SIZE ? size : CIK_SDMA_COPY_MAX_SIZE; @@ -172,9 +172,9 @@ static void cik_sdma_copy_tile(struct si_context *ctx, r600_need_dma_space(&ctx->b, ncopy * 12); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rsrc->resource, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rdst->resource, - RADEON_USAGE_WRITE, RADEON_PRIO_MIN); + RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE); copy_height = size * 4 / pitch; for (i = 0; i < ncopy; i++) { diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index e1849bad933..c6605346771 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -297,7 +297,7 @@ static void si_launch_grid( radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, shader->scratch_bo, RADEON_USAGE_READWRITE, - RADEON_PRIO_SHADER_RESOURCE_RW); + RADEON_PRIO_SCRATCH_BUFFER); scratch_buffer_va = shader->scratch_bo->gpu_address; } @@ -311,7 +311,7 @@ static void si_launch_grid( kernel_args_va += kernel_args_offset; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, input_buffer, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER); si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va); si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0)); @@ -340,7 +340,7 @@ static void si_launch_grid( } radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_SHADER_RESOURCE_RW); + RADEON_PRIO_COMPUTE_GLOBAL); } /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID @@ -362,7 +362,7 @@ static void si_launch_grid( shader_va += pc; #endif radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, shader->bo, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8); si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40); diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 32ab6a9dcbf..d4bd7b28cf3 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -160,7 +160,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, /* This must be done after need_cs_space. */ radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE, - RADEON_PRIO_MIN); + RADEON_PRIO_CP_DMA); /* Flush the caches for the first copy only. * Also wait for the previous CP DMA operations. */ @@ -240,9 +240,9 @@ void si_copy_buffer(struct si_context *sctx, /* This must be done after r600_need_cs_space. */ radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, RADEON_PRIO_CP_DMA); radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, - RADEON_USAGE_WRITE, RADEON_PRIO_MIN); + RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA); si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags); diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index b07ab3b94ac..74ec7cccba8 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -118,7 +118,7 @@ static bool si_upload_descriptors(struct si_context *sctx, util_memcpy_cpu_to_le32(ptr, desc->list, list_size); radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, desc->buffer, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS); desc->list_dirty = false; desc->pointer_dirty = true; @@ -138,17 +138,6 @@ static void si_release_sampler_views(struct si_sampler_views *views) si_release_descriptors(&views->desc); } -static enum radeon_bo_priority si_get_resource_ro_priority(struct r600_resource *res) -{ - if (res->b.b.target == PIPE_BUFFER) - return RADEON_PRIO_SHADER_BUFFER_RO; - - if (res->b.b.nr_samples > 1) - return RADEON_PRIO_SHADER_TEXTURE_MSAA; - - return RADEON_PRIO_SHADER_TEXTURE_RO; -} - static void si_sampler_views_begin_new_cs(struct si_context *sctx, struct si_sampler_views *views) { @@ -165,13 +154,13 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx, radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ, - si_get_resource_ro_priority(rview->resource)); + r600_get_sampler_view_priority(rview->resource)); } if (!views->desc.buffer) return; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, - RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); + RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS); } static void si_set_sampler_view(struct si_context *sctx, unsigned shader, @@ -190,7 +179,7 @@ static void si_set_sampler_view(struct si_context *sctx, unsigned shader, if (rview->resource) radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ, - si_get_resource_ro_priority(rview->resource)); + r600_get_sampler_view_priority(rview->resource)); pipe_sampler_view_reference(&views->views[slot], view); memcpy(views->desc.list + slot*8, view_desc, 8*4); @@ -270,7 +259,7 @@ static void si_sampler_states_begin_new_cs(struct si_context *sctx, if (!states->desc.buffer) return; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, states->desc.buffer, - RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA); + RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS); } static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, @@ -348,7 +337,7 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx, return; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, buffers->desc.buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_SHADER_DATA); + RADEON_PRIO_DESCRIPTORS); } /* VERTEX BUFFERS */ @@ -369,14 +358,14 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx) radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)sctx->vertex_buffer[vb].buffer, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); + RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); } if (!desc->buffer) return; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_DATA); + RADEON_PRIO_DESCRIPTORS); } static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) @@ -403,7 +392,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_DATA); + RADEON_PRIO_DESCRIPTORS); assert(count <= SI_NUM_VERTEX_BUFFERS); @@ -447,7 +436,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) if (!bound[ve->vertex_buffer_index]) { radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)vb->buffer, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); + RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); bound[ve->vertex_buffer_index] = true; } } @@ -870,7 +859,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_BUFFER_RO); + RADEON_PRIO_SAMPLER_BUFFER); } } } @@ -1017,10 +1006,10 @@ void si_init_all_descriptors(struct si_context *sctx) for (i = 0; i < SI_NUM_SHADERS; i++) { si_init_buffer_resources(&sctx->const_buffers[i], SI_NUM_CONST_BUFFERS, SI_SGPR_CONST, - RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO); + RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER); si_init_buffer_resources(&sctx->rw_buffers[i], SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS, - RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW); + RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT); si_init_descriptors(&sctx->samplers[i].views.desc, SI_SGPR_RESOURCE, 8, SI_NUM_SAMPLER_VIEWS); diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c index 309ae04424a..3d980fb67b8 100644 --- a/src/gallium/drivers/radeonsi/si_dma.c +++ b/src/gallium/drivers/radeonsi/si_dma.c @@ -79,9 +79,9 @@ static void si_dma_copy_buffer(struct si_context *ctx, r600_need_dma_space(&ctx->b, ncopy * 5); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ, - RADEON_PRIO_MIN); + RADEON_PRIO_SDMA_BUFFER); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE, - RADEON_PRIO_MIN); + RADEON_PRIO_SDMA_BUFFER); for (i = 0; i < ncopy; i++) { csize = size < max_csize ? size : max_csize; @@ -178,9 +178,9 @@ static void si_dma_copy_tile(struct si_context *ctx, r600_need_dma_space(&ctx->b, ncopy * 9); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rsrc->resource, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE); radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rdst->resource, - RADEON_USAGE_WRITE, RADEON_PRIO_MIN); + RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE); for (i = 0; i < ncopy; i++) { cheight = copy_height; diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index b1834afa796..f16933c5f98 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -140,7 +140,8 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state) struct r600_resource *ib = state->indirect_buffer; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, ib, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, + RADEON_PRIO_IB2); radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0)); radeon_emit(cs, ib->gpu_address); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d74f6e896c4..5d4e579b392 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2238,7 +2238,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, tex->cmask_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_COLOR_META); + RADEON_PRIO_CMASK); } radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, @@ -2285,7 +2285,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom if (zb->db_htile_data_base) { radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_DEPTH_META); + RADEON_PRIO_HTILE); } radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); @@ -3391,7 +3391,7 @@ static void si_init_config(struct si_context *sctx) if (sctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40); si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_DATA); + RADEON_PRIO_BORDER_COLORS); si_pm4_upload_indirect_buffer(sctx, pm4); sctx->init_config = pm4; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 6d8e0e509bf..fb65eb3ce2d 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -353,7 +353,7 @@ static void si_emit_scratch_reloc(struct si_context *sctx) if (sctx->scratch_buffer) { radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, sctx->scratch_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_SHADER_RESOURCE_RW); + RADEON_PRIO_SCRATCH_BUFFER); } sctx->emit_scratch_reloc = false; @@ -467,7 +467,7 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ, - RADEON_PRIO_MIN); + RADEON_PRIO_SO_FILLED_SIZE); } /* draw packet */ @@ -521,7 +521,7 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource *)info->indirect, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT); } if (info->indexed) { @@ -531,7 +531,7 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource *)ib->buffer, - RADEON_USAGE_READ, RADEON_PRIO_MIN); + RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER); if (info->indirect) { uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; @@ -883,7 +883,7 @@ void si_trace_emit(struct si_context *sctx) sctx->trace_id++; radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, sctx->trace_buf, - RADEON_USAGE_READWRITE, RADEON_PRIO_MIN); + RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE); radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | S_370_WR_CONFIRM(1) | diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index b5e14ead160..31c0ab95464 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -103,7 +103,7 @@ static void si_shader_ls(struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); /* We need at least 2 components for LS. * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */ @@ -138,7 +138,7 @@ static void si_shader_hs(struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); num_user_sgprs = SI_TCS_NUM_USER_SGPR; num_sgprs = shader->num_sgprs; @@ -173,7 +173,7 @@ static void si_shader_es(struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); if (shader->selector->type == PIPE_SHADER_VERTEX) { vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0; @@ -279,7 +279,7 @@ static void si_shader_gs(struct si_shader *shader) S_028B90_ENABLE(gs_num_invocations > 0)); va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40); @@ -327,7 +327,7 @@ static void si_shader_vs(struct si_shader *shader) si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0); va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); if (shader->is_gs_copy_shader) { vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */ @@ -458,7 +458,7 @@ static void si_shader_ps(struct si_shader *shader) si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask); va = shader->bo->gpu_address; - si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA); + si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40); -- cgit v1.2.3