From 13aa8d3da92bd83abc8d5212764a15b1217e93bd Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 15 Aug 2017 17:51:05 +0200 Subject: radeonsi: don't use CLEAR_STATE on SI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes random hangs with Unigine Valley. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102201 Fixes: 064550238ef0 ("radeonsi: use CLEAR_STATE to initialize some registers") Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_pipe.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/gallium/drivers/radeonsi/si_pipe.c') diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index cac1d015593..80a77a8f1f2 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1067,6 +1067,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->tess_offchip_block_dw_size = sscreen->b.family == CHIP_HAWAII ? 4096 : 8192; + /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs + * on SI. */ + sscreen->has_clear_state = sscreen->b.chip_class >= CIK; + sscreen->has_distributed_tess = sscreen->b.chip_class >= VI && sscreen->b.info.max_se >= 2; -- cgit v1.2.3