From 9c21002f6ed0621fbd68f413eceb58a89ace7275 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 20 Jun 2018 18:15:36 -0500 Subject: radeonsi: handle non-clearable DCC buffers as MSAA resolve dst This is reproducible on Stoney, but other chips may be affected too. Cc 18.1 Reviewed-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_clear.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gallium/drivers/radeonsi/si_clear.c') diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 72319b3eca2..53c255c5808 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -479,7 +479,7 @@ static void si_do_fast_color_clear(struct si_context *sctx, if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR)) continue; - /* This can only occur with MSAA. */ + /* This can happen with mipmapping or MSAA. */ if (sctx->chip_class == VI && !tex->surface.u.legacy.level[level].dcc_fast_clear_size) continue; -- cgit v1.2.3