From d5c7ea3b83168d8fd77ed4bd834901209e1d47da Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Sun, 23 Oct 2016 15:51:46 +0200 Subject: gallium/radeon: decrease the size of radeon_surf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeon/r600_texture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/radeon/r600_texture.c') diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index a89b2850e4c..c9c87c7dbb0 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -929,7 +929,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) rtex->surface.bpe, rtex->resource.b.b.nr_samples, rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format)); - fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, " + fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, " "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n", rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw, rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea, @@ -959,7 +959,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) rtex->tc_compatible_htile); if (rtex->dcc_offset) { - fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%"PRIu64"\n", + fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%u\n", rtex->dcc_offset, rtex->surface.dcc_size, rtex->surface.dcc_alignment); for (i = 0; i <= rtex->resource.b.b.last_level; i++) -- cgit v1.2.3