From 955505f6ff1c8bba7eb142200d3bd065eb4d2297 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 7 Aug 2014 21:14:31 +0200 Subject: radeonsi: fix CMASK and HTILE allocation on Tahiti MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeon/r600_texture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/radeon/r600_texture.c') diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 6c846241cb0..d07c9a0c500 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -389,7 +389,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, struct r600_cmask_info *out) { unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes; - unsigned num_pipes = rscreen->info.r600_num_tile_pipes; + unsigned num_pipes = rscreen->tiling_info.num_channels; unsigned cl_width, cl_height; switch (num_pipes) { @@ -486,7 +486,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen, { unsigned cl_width, cl_height, width, height; unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; - unsigned num_pipes = rscreen->info.r600_num_tile_pipes; + unsigned num_pipes = rscreen->tiling_info.num_channels; /* HTILE is broken with 1D tiling on old kernels and CIK. */ if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D && -- cgit v1.2.3