From 272b50a6f43adc6aa49da778119af9b219c170ae Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 27 Oct 2016 23:48:44 +0200 Subject: radeonsi/gfx9: do DCC clears on non-mipmapped textures only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeon/r600_texture.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/radeon/r600_texture.c') diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 1838de4f4d4..5b1f941521b 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -2417,7 +2417,7 @@ void vi_dcc_clear_level(struct r600_common_context *rctx, unsigned level, unsigned clear_value) { struct pipe_resource *dcc_buffer; - uint64_t dcc_offset; + uint64_t dcc_offset, clear_size; assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels); @@ -2429,10 +2429,18 @@ void vi_dcc_clear_level(struct r600_common_context *rctx, dcc_offset = rtex->dcc_offset; } - dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; + if (rctx->chip_class >= GFX9) { + /* Mipmap level clears aren't implemented. */ + assert(rtex->resource.b.b.last_level == 0); + /* MSAA needs a different clear size. */ + assert(rtex->resource.b.b.nr_samples <= 1); + clear_size = rtex->surface.dcc_size; + } else { + dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; + clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size; + } - rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset, - rtex->surface.u.legacy.level[level].dcc_fast_clear_size, + rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset, clear_size, clear_value, R600_COHERENCY_CB_META); } -- cgit v1.2.3