From 50283109aa2b1a3fd92e92eb1c85426444ef508e Mon Sep 17 00:00:00 2001 From: Nicolai Hähnle Date: Fri, 25 Aug 2017 09:04:40 +0200 Subject: radeonsi: ensure cache flushes happen before SET_PREDICATION packets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The data is read when the render_cond_atom is emitted, so we must delay emitting the atom until after the flush. Fixes: 0fe0320dc074 ("radeonsi: use optimal packet order when doing a pipeline sync") Reviewed-by: Marek Olšák --- src/gallium/drivers/radeon/r600_query.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/radeon/r600_query.c') diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c index f937612bc1f..03ff1018a71 100644 --- a/src/gallium/drivers/radeon/r600_query.c +++ b/src/gallium/drivers/radeon/r600_query.c @@ -1835,11 +1835,14 @@ static void r600_render_condition(struct pipe_context *ctx, /* Settings this in the render cond atom is too late, * so set it here. */ - rctx->flags |= rctx->screen->barrier_flags.L2_to_cp; - - atom->num_dw = 5; + rctx->flags |= rctx->screen->barrier_flags.L2_to_cp | + R600_CONTEXT_FLUSH_FOR_RENDER_COND; rctx->render_cond_force_off = old_force_off; + } + + if (needs_workaround) { + atom->num_dw = 5; } else { for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous) atom->num_dw += (qbuf->results_end / rquery->result_size) * 5; -- cgit v1.2.3