From 95ed0e9b6b445c70e920d340818fc0f84d45233e Mon Sep 17 00:00:00 2001 From: Vadim Girlin Date: Mon, 7 May 2012 12:47:47 +0400 Subject: radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions Signed-off-by: Vadim Girlin --- src/gallium/drivers/radeon/R600Instructions.td | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/gallium/drivers/radeon/R600Instructions.td') diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 16ed4fbc51f..0a73b5cfbf0 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -387,6 +387,27 @@ def CNDE_INT : R600_3OP < /* Texture instructions */ + +def TEX_LD : R600_TEX < + 0x03, "TEX_LD", + [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_TEXTURE_RESINFO : R600_TEX < + 0x04, "TEX_GET_TEXTURE_RESINFO", + [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_GRADIENTS_H : R600_TEX < + 0x07, "TEX_GET_GRADIENTS_H", + [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_GRADIENTS_V : R600_TEX < + 0x08, "TEX_GET_GRADIENTS_V", + [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + def TEX_SAMPLE : R600_TEX < 0x10, "TEX_SAMPLE", [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))] -- cgit v1.2.3