From 92823fb72abf1539bdb545fedc5525e9fc0b04cc Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 18 Jul 2012 12:26:45 -0400 Subject: radeon/llvm: Move lowering of SETCC node to R600ISelLowering SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector. --- src/gallium/drivers/radeon/R600ISelLowering.cpp | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp') diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index b903b5b58bb..9c92498bfdc 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -38,6 +38,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::SETCC, MVT::i32, Custom); + setSchedulingPreference(Sched::VLIW); } @@ -273,6 +275,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); case ISD::ROTL: return LowerROTL(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::SETCC: return LowerSETCC(Op, DAG); } } @@ -394,3 +397,28 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); } + +SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const +{ + SDValue Cond; + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue CC = Op.getOperand(2); + DebugLoc DL = Op.getDebugLoc(); + assert(Op.getValueType() == MVT::i32); + Cond = DAG.getNode( + ISD::SELECT_CC, + Op.getDebugLoc(), + MVT::i32, + LHS, RHS, + DAG.getConstant(-1, MVT::i32), + DAG.getConstant(0, MVT::i32), + CC); + Cond = DAG.getNode( + ISD::AND, + DL, + MVT::i32, + DAG.getConstant(1, MVT::i32), + Cond); + return Cond; +} -- cgit v1.2.3