From 667cdba2118cf82e0027bf44314c9d1334d00840 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Fri, 25 May 2012 10:59:52 -0400
Subject: radeon/llvm: Use a custom inserter to lower FNEG

---
 src/gallium/drivers/radeon/AMDILInstructions.td | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'src/gallium/drivers/radeon/AMDILInstructions.td')

diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 869c2bb6af2..0197e9418f3 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -50,7 +50,6 @@ def INTTOANY_i16: OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins GPRI32:$src0),
 //===---------------------------------------------------------------------===//
 // Signed 32bit integer math instructions start here
 //===---------------------------------------------------------------------===//
-defm NEGATE     : UnaryOpMCi32<IL_OP_I_NEGATE, IL_inegate>;
 // get rid of the addri via the tablegen instead of custom lowered instruction
 defm EADD   : BinaryOpMCi32<IL_OP_I_ADD, adde>;
 def INTTOANY_i32: OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins GPRI32:$src0),
@@ -238,10 +237,6 @@ defm NEAR : UnaryOpMCf32<IL_OP_ROUND_NEAR, fnearbyint>;
 defm RND_Z : UnaryOpMCf32<IL_OP_ROUND_ZERO, ftrunc>;
 
 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
-def NEG_f32         : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst),
-  (ins GPRF32:$src0),
-    !strconcat(IL_OP_MOV.Text, " $dst, $src0"),
-    [(set GPRF32:$dst, (fneg GPRF32:$src0))]>;
 def INTTOANY_f32    : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst),
   (ins GPRI32:$src0),
     !strconcat(IL_OP_MOV.Text, " $dst, $src0"),
-- 
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