From cd287301ec598d2811f3f85c03d23bae01be2359 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 19 Jun 2012 18:47:18 -0400 Subject: radeon/llvm: Use the VLIW Scheduler for R600->NI It's not optimal, but it's better than the register pressure scheduler that was previously being used. The VLIW scheduler currently ignores all the complicated instruction groups restrictions and just tries to fill the instruction groups with as many instructions as possible. Though, it does know enough not to put two trans only instructions in the same group. We are able to ignore the instruction group restrictions in the LLVM backend, because the finalizer in r600_asm.c will fix any illegal instruction groups the backend generates. Enabling the VLIW scheduler improved the run time for a sha1 compute shader by about 50%. I'm not sure what the impact will be for graphics shaders. I tested Lightsmark with the VLIW scheduler enabled and the framerate was about the same, but it might help apps that use really big shaders. --- src/gallium/drivers/radeon/AMDGPUInstructions.td | 1 + 1 file changed, 1 insertion(+) (limited to 'src/gallium/drivers/radeon/AMDGPUInstructions.td') diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 9ec9c4d0356..d6897d57060 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -21,6 +21,7 @@ class AMDGPUInst pattern> : Instructio let InOperandList = ins; let AsmString = asm; let Pattern = pattern; + let Itinerary = NullALU; let TSFlags{42-40} = Gen; let TSFlags{63-48} = AMDILOp; } -- cgit v1.2.3