From bee2b96b02161cf75cfe17f7d30d14f2b838423f Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 20 Feb 2014 15:39:35 +0100 Subject: r600g,radeonsi: set priorities for relocations --- src/gallium/drivers/r600/r600_state.c | 54 ++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 14 deletions(-) (limited to 'src/gallium/drivers/r600/r600_state.c') diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 3e3b0ddd9a5..e0e75c6b28a 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1405,7 +1405,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)cb[i]->base.texture, - RADEON_USAGE_READWRITE); + RADEON_USAGE_READWRITE, + cb[i]->base.texture->nr_samples > 1 ? + RADEON_PRIO_COLOR_BUFFER_MSAA : + RADEON_PRIO_COLOR_BUFFER); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc); @@ -1415,7 +1418,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, cb[i]->cb_buffer_fmask, - RADEON_USAGE_READWRITE); + RADEON_USAGE_READWRITE, + cb[i]->base.texture->nr_samples > 1 ? + RADEON_PRIO_COLOR_BUFFER_MSAA : + RADEON_PRIO_COLOR_BUFFER); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc); @@ -1425,7 +1431,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, cb[i]->cb_buffer_cmask, - RADEON_USAGE_READWRITE); + RADEON_USAGE_READWRITE, + cb[i]->base.texture->nr_samples > 1 ? + RADEON_PRIO_COLOR_BUFFER_MSAA : + RADEON_PRIO_COLOR_BUFFER); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc); } @@ -1461,7 +1470,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a unsigned reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)state->zsbuf->texture, - RADEON_USAGE_READWRITE); + RADEON_USAGE_READWRITE, + surf->base.texture->nr_samples > 1 ? + RADEON_PRIO_DEPTH_BUFFER_MSAA : + RADEON_PRIO_DEPTH_BUFFER); r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, surf->pa_su_poly_offset_db_fmt_cntl); @@ -1554,7 +1566,8 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); - reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE); + reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, + RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META); cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); cs->buf[cs->cdw++] = reloc_idx; } else { @@ -1652,7 +1665,8 @@ static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); } } @@ -1684,7 +1698,8 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, } radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); radeon_emit(cs, (buffer_id_base + buffer_index) * 7); @@ -1699,7 +1714,8 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO)); dirty_mask &= ~(1 << buffer_index); } @@ -1747,7 +1763,10 @@ static void r600_emit_sampler_views(struct r600_context *rctx, radeon_emit_array(cs, rview->tex_resource_words, 7); reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource, - RADEON_USAGE_READ); + RADEON_USAGE_READ, + rview->tex_resource->b.b.nr_samples > 1 ? + RADEON_PRIO_SHADER_TEXTURE_MSAA : + RADEON_PRIO_SHADER_TEXTURE_RO); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); @@ -1874,7 +1893,8 @@ static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, + RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA)); } static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) @@ -1923,7 +1943,9 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, (r600_resource_va(screen, &rbuffer->b.b)) >> 8); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, + RADEON_USAGE_READWRITE, + RADEON_PRIO_SHADER_RESOURCE_RW)); r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, state->esgs_ring.buffer_size >> 8); @@ -1931,7 +1953,9 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, (r600_resource_va(screen, &rbuffer->b.b)) >> 8); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READWRITE)); + radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, + RADEON_USAGE_READWRITE, + RADEON_PRIO_SHADER_RESOURCE_RW)); r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, state->gsvs_ring.buffer_size >> 8); } else { @@ -2846,8 +2870,10 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, cheight = cheight > copy_height ? copy_height : cheight; size = (cheight * pitch) >> 2; /* emit reloc before writting cs so that cs is always in consistent state */ - r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ); - r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ, + RADEON_PRIO_MIN); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE, + RADEON_PRIO_MIN); cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size); cs->buf[cs->cdw++] = base >> 8; cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) | -- cgit v1.2.3