From 2f0811054fd53db776531428eef1f6960f180f38 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 18:09:10 +0100 Subject: nouveau: recalc sub width and height for each mipmap level --- src/gallium/drivers/nv04/nv04_surface_2d.c | 39 ++++++++++++++++++------------ 1 file changed, 23 insertions(+), 16 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index 1b5d980468d..a8aa12cb8f4 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -104,11 +104,7 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst)); const unsigned max_w = 1024; const unsigned max_h = 1024; - const unsigned sub_w = w > max_w ? max_w : w; - const unsigned sub_h = h > max_h ? max_h : h; - unsigned cx = 0; - unsigned cy = 0; - int i, offset = 0; + int i, src_offset = src->offset, dst_offset = dst->offset, src_stride = src->stride; /* POT or GTFO */ assert(!(w & (w - 1)) && !(h & (h - 1))); @@ -116,10 +112,6 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1); OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); - OUT_RING (chan, nv04_surface_format(dst->format) | - log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | - log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1); OUT_RELOCo(chan, src_bo, @@ -129,12 +121,23 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, /* Upload, then swizzle each mipmap level in turn */ for (i=0; itexture->last_level; i++) { + unsigned sub_w, sub_h; + unsigned cx, cy; + + BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); + OUT_RING (chan, nv04_surface_format(dst->format) | + log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | + log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); + + sub_w = w > max_w ? max_w : w; + sub_h = h > max_h ? max_h : h; for (cy = 0; cy < h; cy += sub_h) { for (cx = 0; cx < w; cx += sub_w) { + BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1); - OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(cx, cy) * - dst->block.size + offset, NOUVEAU_BO_GART | + OUT_RELOCl(chan, dst_bo, dst_offset + nv04_swizzle_bits(cx, cy) * + dst->block.size, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); @@ -150,18 +153,22 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4); OUT_RING (chan, sub_h << 16 | sub_w); - OUT_RING (chan, src->stride | + OUT_RING (chan, src_stride | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); - OUT_RELOCl(chan, src_bo, src->offset + cy * src->stride + - cx * src->block.size + offset, NOUVEAU_BO_GART | + OUT_RELOCl(chan, src_bo, src_offset + cy * src_stride + + cx * src->block.size, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RING (chan, 0); } } - /* FIXME: need to know how many bytes per pixel */ - offset += align(w * h * 2 /*src->block.size*/, 64); + /* FIXME: need to find next offset for both source and dest */ + src_offset += w * h * dst->block.size; + /*src_offset = align(src_offset, 64);*/ + dst_offset += w * h * dst->block.size; + /*dst_offset = align(dst_offset, 64);*/ + src_stride >>= 1; w >>= 1; h >>= 1; } -- cgit v1.2.3 From 02401cbaf021833c77c501d697d912f295546f58 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 18:44:08 +0100 Subject: nouveau: dst offset is correct --- src/gallium/drivers/nv04/nv04_surface_2d.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index a8aa12cb8f4..ad11b2fd45a 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -163,11 +163,9 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, } } - /* FIXME: need to find next offset for both source and dest */ - src_offset += w * h * dst->block.size; - /*src_offset = align(src_offset, 64);*/ + /* FIXME: need to find next offset for source */ + /*src_offset += w * h * src->block.size;*/ dst_offset += w * h * dst->block.size; - /*dst_offset = align(dst_offset, 64);*/ src_stride >>= 1; w >>= 1; h >>= 1; -- cgit v1.2.3 From 0cd28c4a1b5a48b28be256a808f310fe995e9c7e Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 21:20:06 +0100 Subject: nouveau: revert most parts of recent mipmap+swizzle stuff. We only need to find right src and dst offset for given mipmap level. --- src/gallium/drivers/nv04/nv04_surface_2d.c | 93 ++++++++++++++---------------- 1 file changed, 43 insertions(+), 50 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index ad11b2fd45a..538f8233197 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -104,7 +104,10 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, struct nouveau_bo *dst_bo = ctx->nvws->get_bo(ctx->buf(dst)); const unsigned max_w = 1024; const unsigned max_h = 1024; - int i, src_offset = src->offset, dst_offset = dst->offset, src_stride = src->stride; + const unsigned sub_w = w > max_w ? max_w : w; + const unsigned sub_h = h > max_h ? max_h : h; + unsigned cx, cy; + int i, src_offset = src->offset, dst_offset = dst->offset; /* POT or GTFO */ assert(!(w & (w - 1)) && !(h & (h - 1))); @@ -113,62 +116,52 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); + OUT_RING (chan, nv04_surface_format(dst->format) | + log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | + log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); + BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1); OUT_RING (chan, swzsurf->handle); - /* Upload, then swizzle each mipmap level in turn */ - for (i=0; itexture->last_level; i++) { - unsigned sub_w, sub_h; - unsigned cx, cy; - - BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); - OUT_RING (chan, nv04_surface_format(dst->format) | - log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | - log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); - - sub_w = w > max_w ? max_w : w; - sub_h = h > max_h ? max_h : h; - - for (cy = 0; cy < h; cy += sub_h) { - for (cx = 0; cx < w; cx += sub_w) { - - BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1); - OUT_RELOCl(chan, dst_bo, dst_offset + nv04_swizzle_bits(cx, cy) * - dst->block.size, NOUVEAU_BO_GART | - NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - - BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); - OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); - OUT_RING (chan, nv04_scaled_image_format(src->format)); - OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY); - OUT_RING (chan, 0); - OUT_RING (chan, sub_h << 16 | sub_w); - OUT_RING (chan, 0); - OUT_RING (chan, sub_h << 16 | sub_w); - OUT_RING (chan, 1 << 20); - OUT_RING (chan, 1 << 20); - - BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4); - OUT_RING (chan, sub_h << 16 | sub_w); - OUT_RING (chan, src_stride | - NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | - NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); - OUT_RELOCl(chan, src_bo, src_offset + cy * src_stride + - cx * src->block.size, NOUVEAU_BO_GART | - NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); - OUT_RING (chan, 0); - } - } - - /* FIXME: need to find next offset for source */ - /*src_offset += w * h * src->block.size;*/ + /* FIXME: Find right src and dst offset, given mipmap level */ + for (i=0; ilevel; i++) { + src_offset += w * h * src->block.size; dst_offset += w * h * dst->block.size; - src_stride >>= 1; - w >>= 1; - h >>= 1; + } + + for (cy = 0; cy < h; cy += sub_h) { + for (cx = 0; cx < w; cx += sub_w) { + + BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1); + OUT_RELOCl(chan, dst_bo, dst_offset + nv04_swizzle_bits(cx, cy) * + dst->block.size, NOUVEAU_BO_GART | + NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + + BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9); + OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE); + OUT_RING (chan, nv04_scaled_image_format(src->format)); + OUT_RING (chan, NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY); + OUT_RING (chan, 0); + OUT_RING (chan, sub_h << 16 | sub_w); + OUT_RING (chan, 0); + OUT_RING (chan, sub_h << 16 | sub_w); + OUT_RING (chan, 1 << 20); + OUT_RING (chan, 1 << 20); + + BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SIZE, 4); + OUT_RING (chan, sub_h << 16 | sub_w); + OUT_RING (chan, src->stride | + NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | + NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); + OUT_RELOCl(chan, src_bo, src_offset + cy * src->stride + + cx * src->block.size, NOUVEAU_BO_GART | + NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RING (chan, 0); + } } return 0; -- cgit v1.2.3 From fa9fcf5e8fc1a1fbd25b0943050c51104acb0397 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 21:22:29 +0100 Subject: nouveau: do not forget to half dimension. --- src/gallium/drivers/nv04/nv04_surface_2d.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index 538f8233197..63f212556f7 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -106,7 +106,7 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, const unsigned max_h = 1024; const unsigned sub_w = w > max_w ? max_w : w; const unsigned sub_h = h > max_h ? max_h : h; - unsigned cx, cy; + unsigned cx, cy, level_w, level_h; int i, src_offset = src->offset, dst_offset = dst->offset; /* POT or GTFO */ @@ -128,9 +128,13 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, OUT_RING (chan, swzsurf->handle); /* FIXME: Find right src and dst offset, given mipmap level */ + level_w = w; + level_h = h; for (i=0; ilevel; i++) { - src_offset += w * h * src->block.size; - dst_offset += w * h * dst->block.size; + src_offset += level_w * level_h * src->block.size; + dst_offset += level_w * level_h * dst->block.size; + level_w >>= 1; + level_h >>= 1; } for (cy = 0; cy < h; cy += sub_h) { -- cgit v1.2.3 From 53069cbf290c7de7cc1bf813815e8ef7d5d886a4 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 21:57:40 +0100 Subject: nouveau: we already have the right src offset --- src/gallium/drivers/nv04/nv04_surface_2d.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index 63f212556f7..d220c21c49d 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -107,7 +107,7 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, const unsigned sub_w = w > max_w ? max_w : w; const unsigned sub_h = h > max_h ? max_h : h; unsigned cx, cy, level_w, level_h; - int i, src_offset = src->offset, dst_offset = dst->offset; + int i, dst_offset = dst->offset; /* POT or GTFO */ assert(!(w & (w - 1)) && !(h & (h - 1))); @@ -131,7 +131,6 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, level_w = w; level_h = h; for (i=0; ilevel; i++) { - src_offset += level_w * level_h * src->block.size; dst_offset += level_w * level_h * dst->block.size; level_w >>= 1; level_h >>= 1; @@ -161,7 +160,7 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, OUT_RING (chan, src->stride | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER | NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE); - OUT_RELOCl(chan, src_bo, src_offset + cy * src->stride + + OUT_RELOCl(chan, src_bo, src->offset + cy * src->stride + cx * src->block.size, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RING (chan, 0); -- cgit v1.2.3 From 7b66b24c2ea127aa8f58f38a0cf4e834b58c2aa7 Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 22:04:56 +0100 Subject: nouveau: stop with 0 dimension --- src/gallium/drivers/nv04/nv04_surface_2d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index d220c21c49d..ffb17ea4cac 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -130,7 +130,7 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, /* FIXME: Find right src and dst offset, given mipmap level */ level_w = w; level_h = h; - for (i=0; ilevel; i++) { + for (i=0; ilevel && level_w && level_h; i++) { dst_offset += level_w * level_h * dst->block.size; level_w >>= 1; level_h >>= 1; -- cgit v1.2.3 From 24c379badba888bd58cd759865e454e02235c65a Mon Sep 17 00:00:00 2001 From: Patrice Mandin Date: Tue, 10 Feb 2009 22:22:06 +0100 Subject: nouveau: revert all my changes here, not the right way --- src/gallium/drivers/nv04/nv04_surface_2d.c | 31 +++++++++--------------------- 1 file changed, 9 insertions(+), 22 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index ffb17ea4cac..85308496895 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -1,7 +1,6 @@ #include "pipe/p_context.h" #include "pipe/p_format.h" #include "util/u_memory.h" -#include "util/u_math.h" #include "nouveau/nouveau_winsys.h" #include "nouveau/nouveau_util.h" @@ -106,8 +105,8 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, const unsigned max_h = 1024; const unsigned sub_w = w > max_w ? max_w : w; const unsigned sub_h = h > max_h ? max_h : h; - unsigned cx, cy, level_w, level_h; - int i, dst_offset = dst->offset; + unsigned cx = 0; + unsigned cy = 0; /* POT or GTFO */ assert(!(w & (w - 1)) && !(h & (h - 1))); @@ -118,29 +117,19 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1); OUT_RING (chan, nv04_surface_format(dst->format) | - log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | - log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); - + log2i(w) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT | + log2i(h) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT); + BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1); OUT_RING (chan, swzsurf->handle); - /* FIXME: Find right src and dst offset, given mipmap level */ - level_w = w; - level_h = h; - for (i=0; ilevel && level_w && level_h; i++) { - dst_offset += level_w * level_h * dst->block.size; - level_w >>= 1; - level_h >>= 1; - } - for (cy = 0; cy < h; cy += sub_h) { for (cx = 0; cx < w; cx += sub_w) { - BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1); - OUT_RELOCl(chan, dst_bo, dst_offset + nv04_swizzle_bits(cx, cy) * + OUT_RELOCl(chan, dst_bo, dst->offset + nv04_swizzle_bits(cx, cy) * dst->block.size, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -259,8 +248,7 @@ nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst, assert(src->format == dst->format); /* Setup transfer to swizzle the texture to vram if needed */ - /* FIXME/TODO: check proper limits of this operation */ - if (src_linear ^ dst_linear) { + if (src_linear && !dst_linear && w > 1 && h > 1) { nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h); return; } @@ -268,7 +256,8 @@ nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst, /* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback * to NV_MEMORY_TO_MEMORY_FORMAT in this case. */ - if ((src->offset & 63) || (dst->offset & 63)) { + if ((src->offset & 63) || (dst->offset & 63) || + (src->stride & 63) || (dst->stride & 63)) { nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h); return; } @@ -457,5 +446,3 @@ nv04_surface_2d_init(struct nouveau_winsys *nvws) ctx->fill = nv04_surface_fill; return ctx; } - - -- cgit v1.2.3 From 14d808f8fdc41a26cea5264e47a24c903e54ce93 Mon Sep 17 00:00:00 2001 From: Younes Manton Date: Tue, 10 Feb 2009 16:36:33 -0500 Subject: nouveau: nv40 swizzled mipmap fixes. --- src/gallium/drivers/nv04/nv04_surface_2d.c | 4 ++-- src/gallium/drivers/nv40/nv40_miptree.c | 38 +++++++++++++++++++++--------- src/gallium/drivers/nv40/nv40_screen.c | 2 ++ 3 files changed, 31 insertions(+), 13 deletions(-) (limited to 'src/gallium/drivers/nv04') diff --git a/src/gallium/drivers/nv04/nv04_surface_2d.c b/src/gallium/drivers/nv04/nv04_surface_2d.c index 85308496895..230cfd17dd9 100644 --- a/src/gallium/drivers/nv04/nv04_surface_2d.c +++ b/src/gallium/drivers/nv04/nv04_surface_2d.c @@ -105,8 +105,8 @@ nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx, const unsigned max_h = 1024; const unsigned sub_w = w > max_w ? max_w : w; const unsigned sub_h = h > max_h ? max_h : h; - unsigned cx = 0; - unsigned cy = 0; + unsigned cx; + unsigned cy; /* POT or GTFO */ assert(!(w & (w - 1)) && !(h & (h - 1))); diff --git a/src/gallium/drivers/nv40/nv40_miptree.c b/src/gallium/drivers/nv40/nv40_miptree.c index 9bef23ad1f6..e4f8df910a9 100644 --- a/src/gallium/drivers/nv40/nv40_miptree.c +++ b/src/gallium/drivers/nv40/nv40_miptree.c @@ -10,7 +10,12 @@ nv40_miptree_layout(struct nv40_miptree *mt) struct pipe_texture *pt = &mt->base; uint width = pt->width[0], height = pt->height[0], depth = pt->depth[0]; uint offset = 0; - int nr_faces, l, f, pitch; + int nr_faces, l, f; + uint wide_pitch = pt->tex_usage & (PIPE_TEXTURE_USAGE_SAMPLER | + PIPE_TEXTURE_USAGE_DEPTH_STENCIL | + PIPE_TEXTURE_USAGE_RENDER_TARGET | + PIPE_TEXTURE_USAGE_DISPLAY_TARGET | + PIPE_TEXTURE_USAGE_PRIMARY); if (pt->target == PIPE_TEXTURE_CUBE) { nr_faces = 6; @@ -21,7 +26,6 @@ nv40_miptree_layout(struct nv40_miptree *mt) nr_faces = 1; } - pitch = pt->width[0]; for (l = 0; l <= pt->last_level; l++) { pt->width[l] = width; pt->height[l] = height; @@ -29,11 +33,11 @@ nv40_miptree_layout(struct nv40_miptree *mt) pt->nblocksx[l] = pf_get_nblocksx(&pt->block, width); pt->nblocksy[l] = pf_get_nblocksy(&pt->block, height); - if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) - pitch = pt->nblocksx[l]; - pitch = align(pitch, 64); + if (wide_pitch && (pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) + mt->level[l].pitch = align(pt->width[0] * pt->block.size, 64); + else + mt->level[l].pitch = pt->width[l] * pt->block.size; - mt->level[l].pitch = pitch * pt->block.size; mt->level[l].image_offset = CALLOC(nr_faces, sizeof(unsigned)); @@ -43,10 +47,17 @@ nv40_miptree_layout(struct nv40_miptree *mt) } for (f = 0; f < nr_faces; f++) { - for (l = 0; l <= pt->last_level; l++) { + for (l = 0; l < pt->last_level; l++) { mt->level[l].image_offset[f] = offset; - offset += mt->level[l].pitch * pt->height[l]; + + if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) + offset += align(mt->level[l].pitch * pt->height[l], 64); + else + offset += mt->level[l].pitch * pt->height[l]; } + + mt->level[l].image_offset[f] = offset; + offset += mt->level[l].pitch * pt->height[l]; } mt->total_size = offset; @@ -75,7 +86,8 @@ nv40_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt) mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR; else if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY | - PIPE_TEXTURE_USAGE_DISPLAY_TARGET)) + PIPE_TEXTURE_USAGE_DISPLAY_TARGET | + PIPE_TEXTURE_USAGE_DEPTH_STENCIL)) mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR; else if (pt->tex_usage & PIPE_TEXTURE_USAGE_DYNAMIC) @@ -86,7 +98,11 @@ nv40_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt) case PIPE_FORMAT_A8R8G8B8_UNORM: case PIPE_FORMAT_X8R8G8B8_UNORM: case PIPE_FORMAT_R16_SNORM: + { + if (debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE)) + mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR; break; + } default: mt->base.tex_usage |= NOUVEAU_TEXTURE_USAGE_LINEAR; } @@ -149,8 +165,8 @@ nv40_miptree_release(struct pipe_screen *pscreen, struct pipe_texture **ppt) } if (mt->shadow_tex) { - assert(mt->shadow_surface); - pscreen->tex_surface_release(pscreen, &mt->shadow_surface); + if (mt->shadow_surface) + pscreen->tex_surface_release(pscreen, &mt->shadow_surface); nv40_miptree_release(pscreen, &mt->shadow_tex); } diff --git a/src/gallium/drivers/nv40/nv40_screen.c b/src/gallium/drivers/nv40/nv40_screen.c index 88a329ea245..2372bc84410 100644 --- a/src/gallium/drivers/nv40/nv40_screen.c +++ b/src/gallium/drivers/nv40/nv40_screen.c @@ -214,6 +214,8 @@ nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface) nvscreen->eng2d->copy(nvscreen->eng2d, surface, 0, 0, surface_to_unmap, 0, 0, surface->width, surface->height); + + screen->tex_surface_release(screen, &surface_to_unmap); } } -- cgit v1.2.3