From 8fdb800bdaa28f4ca563829f70e8b187f867c0ac Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 25 Nov 2016 12:25:58 +0100 Subject: gm107/ir: optimize 32-bit CONST load to mov This is not allowed for indirect accesses because the source GPR might be erased by a subsequent instruction (WaR hazard) if we don't emit a read dep bar. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp | 16 ++++++++++++++++ .../drivers/nouveau/codegen/nv50_ir_lowering_gm107.h | 1 + 2 files changed, 17 insertions(+) (limited to 'src/gallium/drivers/nouveau/codegen') diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp index 84ef4e0fb7d..371ebae40c1 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp @@ -61,6 +61,19 @@ GM107LegalizeSSA::handlePFETCH(Instruction *i) i->setSrc(1, NULL); } +void +GM107LegalizeSSA::handleLOAD(Instruction *i) +{ + if (i->src(0).getFile() != FILE_MEMORY_CONST) + return; + if (i->src(0).isIndirect(0)) + return; + if (typeSizeof(i->dType) != 4) + return; + + i->op = OP_MOV; +} + bool GM107LegalizeSSA::visit(Instruction *i) { @@ -68,6 +81,9 @@ GM107LegalizeSSA::visit(Instruction *i) case OP_PFETCH: handlePFETCH(i); break; + case OP_LOAD: + handleLOAD(i); + break; default: break; } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h index 81749bf57ed..d0737beda67 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h @@ -21,6 +21,7 @@ private: virtual bool visit(Instruction *); void handlePFETCH(Instruction *); + void handleLOAD(Instruction *); }; } // namespace nv50_ir -- cgit v1.2.3