From 9254059dd859d6bb8820525910ec028098e788e8 Mon Sep 17 00:00:00 2001 From: Erico Nunes Date: Mon, 22 Jul 2019 00:55:24 +0200 Subject: lima/ppir: fix alignment on regalloc spilling loads The spilling code spills entire vec4 registers regardless of the components used by the spilled uses. The inserted stores code force the 4 components, but these loads were using a variable number of components, causing bugs on loading the spilled registers. Signed-off-by: Erico Nunes Reviewed-by: Qiang Yu --- src/gallium/drivers/lima/ir/pp/regalloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gallium/drivers/lima') diff --git a/src/gallium/drivers/lima/ir/pp/regalloc.c b/src/gallium/drivers/lima/ir/pp/regalloc.c index 62401150e3e..3bd8569cf15 100644 --- a/src/gallium/drivers/lima/ir/pp/regalloc.c +++ b/src/gallium/drivers/lima/ir/pp/regalloc.c @@ -410,7 +410,7 @@ static ppir_alu_node* ppir_update_spilled_src(ppir_compiler *comp, ppir_load_node *load = ppir_node_to_load(load_node); load->index = -comp->prog->stack_size; /* index sizes are negative */ - load->num_components = src->reg->num_components; + load->num_components = 4; ppir_dest *ld_dest = &load->dest; ld_dest->type = ppir_target_pipeline; -- cgit v1.2.3