From ac0051a5075879970f12f614890c9c6d732663b6 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 27 Jul 2017 12:05:56 -0700 Subject: gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle (v3) --- src/gallium/docs/source/screen.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/gallium/docs/source/screen.rst') diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index b968b8c5733..bc0db429b38 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -408,6 +408,9 @@ The integer capabilities: with constant buffers. * ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as an address for indirect register indexing. +* ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports + GL_MESA_tile_raster_order, using the tile_raster_order_* fields in + pipe_rasterizer_state. .. _pipe_capf: -- cgit v1.2.3