From 7fed7c2a7d2fcb3fbb490ad5fbc2db270c33a1f1 Mon Sep 17 00:00:00 2001
From: "Kristian H. Kristensen" <hoegsberg@google.com>
Date: Thu, 19 Sep 2019 17:13:34 -0700
Subject: freedreno/a6xx: Clear sysmem with CP_BLIT

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
---
 src/freedreno/registers/a6xx.xml | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/freedreno')

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 858f2f3c94c..4763c47b7d1 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -963,6 +963,7 @@ to upconvert to 32b float internally?
 	<value value="0x4"  name="R2D_FLOAT32"/>
 	<value value="0x3"  name="R2D_FLOAT16"/>
 	<value value="0x1"  name="R2D_UNORM8_SRGB"/>
+	<value value="0x0"  name="R2D_RAW"/>
 </enum>
 
 <domain name="A6XX" width="32">
@@ -2009,6 +2010,9 @@ to upconvert to 32b float internally?
 		<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
 		<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
 		<bitfield name="SCISSOR" pos="16" type="boolean"/>
+
+		<bitfield name="UNK" low="17" high="18" type="uint"/>
+
 		<!-- required when blitting D24S8/D24X8 -->
 		<bitfield name="D24S8" pos="19" type="boolean"/>
 		<!-- some sort of channel mask, disabled channels are set to zero ? -->
-- 
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