From 8cf297c7b14a04ca587bcbc5cce9e61bcaed5a5a Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 3 Sep 2019 09:49:14 +0200 Subject: radv: do not pass all compiler options to the shader info pass Only the pipeline layout and the shader keys are needed. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 6 +++-- src/amd/vulkan/radv_private.h | 4 ++- src/amd/vulkan/radv_shader_info.c | 51 ++++++++++++++++++++------------------- 3 files changed, 33 insertions(+), 28 deletions(-) (limited to 'src/amd') diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 1b77bd70eec..916f43924c5 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4148,7 +4148,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, radv_nir_shader_info_init(shader_info); for(int i = 0; i < shader_count; ++i) - radv_nir_shader_info_pass(shaders[i], options, shader_info); + radv_nir_shader_info_pass(shaders[i], options->layout, + &options->key, shader_info); for (i = 0; i < MAX_SETS; i++) shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1; @@ -4591,7 +4592,8 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm, ctx.stage = MESA_SHADER_VERTEX; ctx.shader = geom_shader; - radv_nir_shader_info_pass(geom_shader, options, shader_info); + radv_nir_shader_info_pass(geom_shader, options->layout, &options->key, + shader_info); create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index a9c0fc6a97b..bf62ccc9c1d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2129,9 +2129,11 @@ unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class, /* radv_shader_info.h */ struct radv_shader_info; +struct radv_shader_variant_key; void radv_nir_shader_info_pass(const struct nir_shader *nir, - const struct radv_nir_compiler_options *options, + const struct radv_pipeline_layout *layout, + const struct radv_shader_variant_key *key, struct radv_shader_info *info); void radv_nir_shader_info_init(struct radv_shader_info *info); diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 1ff429e63fd..b839d20f1e0 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -377,7 +377,7 @@ gather_info_block(const nir_shader *nir, const nir_block *block, static void gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var, struct radv_shader_info *info, - const struct radv_nir_compiler_options *options) + const struct radv_shader_variant_key *key) { unsigned attrib_count = glsl_count_attribute_slots(var->type, true); int idx = var->data.location; @@ -388,7 +388,7 @@ gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var, for (unsigned i = 0; i < attrib_count; ++i) { unsigned attrib_index = var->data.location + i - VERT_ATTRIB_GENERIC0; - if (options->key.vs.instance_rate_inputs & (1u << attrib_index)) + if (key->vs.instance_rate_inputs & (1u << attrib_index)) info->vs.needs_instance_id = true; } } @@ -466,11 +466,11 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var, static void gather_info_input_decl(const nir_shader *nir, const nir_variable *var, struct radv_shader_info *info, - const struct radv_nir_compiler_options *options) + const struct radv_shader_variant_key *key) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: - gather_info_input_decl_vs(nir, var, info, options); + gather_info_input_decl_vs(nir, var, info, key); break; case MESA_SHADER_FRAGMENT: gather_info_input_decl_ps(nir, var, info); @@ -531,7 +531,7 @@ gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var, static void gather_info_output_decl(const nir_shader *nir, const nir_variable *var, struct radv_shader_info *info, - const struct radv_nir_compiler_options *options) + const struct radv_shader_variant_key *key) { struct radv_vs_output_info *vs_info = NULL; @@ -540,11 +540,11 @@ gather_info_output_decl(const nir_shader *nir, const nir_variable *var, gather_info_output_decl_ps(nir, var, info); break; case MESA_SHADER_VERTEX: - if (!options->key.vs_common_out.as_ls && - !options->key.vs_common_out.as_es) + if (!key->vs_common_out.as_ls && + !key->vs_common_out.as_es) vs_info = &info->vs.outinfo; - if (options->key.vs_common_out.as_ls) + if (key->vs_common_out.as_ls) gather_info_output_decl_ls(nir, var, info); break; case MESA_SHADER_GEOMETRY: @@ -552,7 +552,7 @@ gather_info_output_decl(const nir_shader *nir, const nir_variable *var, gather_info_output_decl_gs(nir, var, info); break; case MESA_SHADER_TESS_EVAL: - if (!options->key.vs_common_out.as_es) + if (!key->vs_common_out.as_es) vs_info = &info->tes.outinfo; break; default: @@ -626,27 +626,28 @@ radv_nir_shader_info_init(struct radv_shader_info *info) void radv_nir_shader_info_pass(const struct nir_shader *nir, - const struct radv_nir_compiler_options *options, + const struct radv_pipeline_layout *layout, + const struct radv_shader_variant_key *key, struct radv_shader_info *info) { struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); - if (options->layout && options->layout->dynamic_offset_count && - (options->layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) { + if (layout && layout->dynamic_offset_count && + (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) { info->loads_push_constants = true; info->loads_dynamic_offsets = true; } nir_foreach_variable(variable, &nir->inputs) - gather_info_input_decl(nir, variable, info, options); + gather_info_input_decl(nir, variable, info, key); nir_foreach_block(block, func->impl) { gather_info_block(nir, block, info); } nir_foreach_variable(variable, &nir->outputs) - gather_info_output_decl(nir, variable, info, options); + gather_info_output_decl(nir, variable, info, key); if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || @@ -654,7 +655,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, gather_xfb_info(nir, info); /* Make sure to export the LayerID if the fragment shader needs it. */ - if (options->key.vs_common_out.export_layer_id) { + if (key->vs_common_out.export_layer_id) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: info->vs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1; @@ -671,7 +672,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, } /* Make sure to export the LayerID if the subpass has multiviews. */ - if (options->key.has_multiview_view_index) { + if (key->has_multiview_view_index) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: info->vs.outinfo.writes_layer = true; @@ -688,7 +689,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, } /* Make sure to export the PrimitiveID if the fragment shader needs it. */ - if (options->key.vs_common_out.export_prim_id) { + if (key->vs_common_out.export_prim_id) { switch (nir->info.stage) { case MESA_SHADER_VERTEX: info->vs.outinfo.export_prim_id = true; @@ -728,18 +729,18 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, info->tes.spacing = nir->info.tess.spacing; info->tes.ccw = nir->info.tess.ccw; info->tes.point_mode = nir->info.tess.point_mode; - info->tes.as_es = options->key.vs_common_out.as_es; - info->tes.export_prim_id = options->key.vs_common_out.export_prim_id; - info->is_ngg = options->key.vs_common_out.as_ngg; + info->tes.as_es = key->vs_common_out.as_es; + info->tes.export_prim_id = key->vs_common_out.export_prim_id; + info->is_ngg = key->vs_common_out.as_ngg; break; case MESA_SHADER_TESS_CTRL: info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; break; case MESA_SHADER_VERTEX: - info->vs.as_es = options->key.vs_common_out.as_es; - info->vs.as_ls = options->key.vs_common_out.as_ls; - info->vs.export_prim_id = options->key.vs_common_out.export_prim_id; - info->is_ngg = options->key.vs_common_out.as_ngg; + info->vs.as_es = key->vs_common_out.as_es; + info->vs.as_ls = key->vs_common_out.as_ls; + info->vs.export_prim_id = key->vs_common_out.export_prim_id; + info->is_ngg = key->vs_common_out.as_ngg; break; default: break; @@ -757,7 +758,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, /* Compute the ESGS item size for VS or TES as ES. */ if ((nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL) && - options->key.vs_common_out.as_es) { + key->vs_common_out.as_es) { struct radv_es_output_info *es_info = nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info; uint32_t max_output_written = 0; -- cgit v1.2.3