From 85769759bf1f3297af36eb9aed67d9de418ca12a Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 4 Jan 2018 16:24:51 +0100 Subject: radv: limit the scissor bug workaround to Vega 10 and Raven Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/amd') diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 0faf8030b49..b0bddd16b39 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1118,7 +1118,12 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer) { uint32_t count = cmd_buffer->state.dynamic.scissor.count; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* Vega10/Raven scissor bug workaround. This must be done before VPORT + * scissor registers are changed. There is also a more efficient but + * more involved alternative workaround. + */ + if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA10 || + cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; si_emit_cache_flush(cmd_buffer); } -- cgit v1.2.3