From dbecbab5aa6fec9d90089ff5e16bc74339edb955 Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Tue, 7 Mar 2017 00:37:46 +0100
Subject: radv/amdgpu: Let addrlib calculate the HTILE parameters.

Still not sure we can support miptrees when sampling from
HTILE enabled textures.

Added the tcCompatible winsys stuff while I'm at it.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/amd/vulkan/winsys/amdgpu')

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index dc596ff0574..89e84d60a3a 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -260,6 +260,30 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 		}
 	}
 
+	if (!is_stencil && AddrSurfInfoIn->flags.depth &&
+	    surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
+		ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
+		ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
+		AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
+		AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
+		AddrHtileIn.height = AddrSurfInfoOut->height;
+		AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
+		AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
+		AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
+		AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
+		AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
+		AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
+
+		ret = AddrComputeHtileInfo(addrlib,
+		                           &AddrHtileIn,
+		                           &AddrHtileOut);
+
+		if (ret == ADDR_OK) {
+			surf->htile_size = AddrHtileOut.htileBytes;
+			surf->htile_slice_size = AddrHtileOut.sliceSize;
+			surf->htile_alignment = AddrHtileOut.baseAlign;
+		}
+	}
 	return 0;
 }
 
@@ -455,6 +479,8 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 	surf->bo_size = 0;
 	surf->dcc_size = 0;
 	surf->dcc_alignment = 1;
+	surf->htile_size = surf->htile_slice_size = 0;
+	surf->htile_alignment = 1;
 
 	/* Calculate texture layout information. */
 	for (level = 0; level <= surf->last_level; level++) {
-- 
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