From dd102405dea022f6c27bc42176f50f3bb2761ae6 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Mon, 14 May 2018 03:01:21 +0200 Subject: radv: Translate logic ops. radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 45 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) (limited to 'src/amd/vulkan/radv_pipeline.c') diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 3d242e05bfd..7a577dae413 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -181,6 +181,47 @@ radv_pipeline_scratch_init(struct radv_device *device, return VK_SUCCESS; } +static uint32_t si_translate_blend_logic_op(VkLogicOp op) +{ + switch (op) { + case VK_LOGIC_OP_CLEAR: + return V_028808_ROP3_CLEAR; + case VK_LOGIC_OP_AND: + return V_028808_ROP3_AND; + case VK_LOGIC_OP_AND_REVERSE: + return V_028808_ROP3_AND_REVERSE; + case VK_LOGIC_OP_COPY: + return V_028808_ROP3_COPY; + case VK_LOGIC_OP_AND_INVERTED: + return V_028808_ROP3_AND_INVERTED; + case VK_LOGIC_OP_NO_OP: + return V_028808_ROP3_NO_OP; + case VK_LOGIC_OP_XOR: + return V_028808_ROP3_XOR; + case VK_LOGIC_OP_OR: + return V_028808_ROP3_OR; + case VK_LOGIC_OP_NOR: + return V_028808_ROP3_NOR; + case VK_LOGIC_OP_EQUIVALENT: + return V_028808_ROP3_EQUIVALENT; + case VK_LOGIC_OP_INVERT: + return V_028808_ROP3_INVERT; + case VK_LOGIC_OP_OR_REVERSE: + return V_028808_ROP3_OR_REVERSE; + case VK_LOGIC_OP_COPY_INVERTED: + return V_028808_ROP3_COPY_INVERTED; + case VK_LOGIC_OP_OR_INVERTED: + return V_028808_ROP3_OR_INVERTED; + case VK_LOGIC_OP_NAND: + return V_028808_ROP3_NAND; + case VK_LOGIC_OP_SET: + return V_028808_ROP3_SET; + default: + unreachable("Unhandled logic op"); + } +} + + static uint32_t si_translate_blend_function(VkBlendOp op) { switch (op) { @@ -600,9 +641,9 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, } blend.cb_color_control = 0; if (vkblend->logicOpEnable) - blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4)); + blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp)); else - blend.cb_color_control |= S_028808_ROP3(0xcc); + blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) | -- cgit v1.2.3