From 5411f470564f6f1c2a55d037103f051cbddd5623 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 25 Jun 2019 16:17:17 +0200 Subject: radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2 Ported from RadeonSI, will be emitted for GFX10 too. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/amd/vulkan/radv_cmd_buffer.c') diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e35ccf80956..29f2e0c8a60 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1876,6 +1876,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) S_028208_BR_Y(framebuffer->height)); if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) { + bool disable_constant_encode = + cmd_buffer->device->physical_device->has_dcc_constant_encode; uint8_t watermark = 4; /* Default value for GFX8. */ /* For optimal DCC performance. */ @@ -1889,7 +1891,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL, S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) | - S_028424_OVERWRITE_COMBINER_WATERMARK(watermark)); + S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | + S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode)); } if (cmd_buffer->device->dfsm_allowed) { -- cgit v1.2.3