From 5b40eab00ad079bcd173234c879d3a8ebf7fe9ec Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 30 Mar 2017 08:13:48 +0100 Subject: radv: add tess ctrl stage barrier workaround for SI. This just ports the workaround from radeonsi. Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/amd/common') diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cb7469168cd..8f56fbf1eb0 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2917,9 +2917,17 @@ static void emit_waitcnt(struct nir_to_llvm_context *ctx, static void emit_barrier(struct nir_to_llvm_context *ctx) { - // TODO tess + /* SI only (thanks to a hw bug workaround): + * The real barrier instruction isn’t needed, because an entire patch + * always fits into a single wave. + */ + if (ctx->options->chip_class == SI && + ctx->stage == MESA_SHADER_TESS_CTRL) { + emit_waitcnt(ctx, LGKM_CNT & VM_CNT); + return; + } ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier", - ctx->voidt, NULL, 0, 0); + ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT); } static void emit_discard_if(struct nir_to_llvm_context *ctx, -- cgit v1.2.3