From ccfcb9d818b40564001b3cf2516367526de26c1d Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 14 May 2019 22:16:20 -0400 Subject: ac: rename SI-CIK-VI to GFX6-GFX7-GFX8 Acked-by: Dave Airlie We already use GFX9 and I don't want us to have confusing naming in the driver. GFXn naming is better from the driver perspective, because it's the real version of the gfx portion of the hw. Also, CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI. It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have nothing to do with GFXn and they have their own version numbers. --- src/amd/common/ac_gpu_info.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src/amd/common/ac_gpu_info.c') diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index e46424dd885..db7f9e47ce1 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -78,7 +78,7 @@ static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info) case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16: return 16; default: - fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n"); + fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n"); assert(!"this should never occur"); return 2; } @@ -323,11 +323,11 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, if (info->family >= CHIP_VEGA10) info->chip_class = GFX9; else if (info->family >= CHIP_TONGA) - info->chip_class = VI; + info->chip_class = GFX8; else if (info->family >= CHIP_BONAIRE) - info->chip_class = CIK; + info->chip_class = GFX7; else if (info->family >= CHIP_TAHITI) - info->chip_class = SI; + info->chip_class = GFX6; else { fprintf(stderr, "amdgpu: Unknown family.\n"); return false; @@ -382,18 +382,18 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_gpu_reset_counter_query = false; info->has_eqaa_surface_allocator = true; info->has_format_bc1_through_bc7 = true; - /* DRM 3.1.0 doesn't flush TC for VI correctly. */ - info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI || + /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */ + info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2; info->has_indirect_compute_dispatch = true; - /* SI doesn't support unaligned loads. */ - info->has_unaligned_shader_loads = info->chip_class != SI; - /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once + /* GFX6 doesn't support unaligned loads. */ + info->has_unaligned_shader_loads = info->chip_class != GFX6; + /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once * these faults are mitigated in software. * Disable sparse mappings on GFX9 due to hangs. */ info->has_sparse_vm_mappings = - info->chip_class >= CIK && info->chip_class <= VI && + info->chip_class >= GFX7 && info->chip_class <= GFX8 && info->drm_minor >= 13; info->has_2d_tiling = true; info->has_read_registers_query = true; @@ -446,7 +446,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->pte_fragment_size = alignment_info.size_local; info->gart_page_size = alignment_info.size_remote; - if (info->chip_class == SI) + if (info->chip_class == GFX6) info->gfx_ib_pad_with_type2 = TRUE; unsigned ib_align = 0; @@ -791,7 +791,7 @@ ac_get_harvested_configs(struct radeon_info *info, assert(rb_per_pkr == 1 || rb_per_pkr == 2); - if (info->chip_class >= CIK) { + if (info->chip_class >= GFX7) { unsigned raster_config_1 = *cik_raster_config_1_p; if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || (!se_mask[2] && !se_mask[3]))) { -- cgit v1.2.3