From b563460b494e9228cf5bb1aa4a70ac2499ad81fe Mon Sep 17 00:00:00 2001
From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 8 Jan 2019 20:08:08 -0500
Subject: radeonsi: enable displayable DCC on Ravens

---
 src/amd/common/ac_gpu_info.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/amd/common/ac_gpu_info.c')

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index d890172227c..c53335bbb7d 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -458,6 +458,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	assert(ib_align);
 	info->ib_start_alignment = ib_align;
 
+	if (info->drm_minor >= 31 &&
+	    (info->family == CHIP_RAVEN ||
+	     info->family == CHIP_RAVEN2)) {
+		if (info->num_render_backends == 1)
+			info->use_display_dcc_unaligned = true;
+		else
+			info->use_display_dcc_with_retile_blit = true;
+	}
 	return true;
 }
 
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