From 7f33e94e43a647d71a9f930cf3180e5abb529edd Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 7 Nov 2017 00:56:13 +0100 Subject: amd/addrlib: update to latest version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle --- src/amd/addrlib/core/addrcommon.h | 14 +-- src/amd/addrlib/core/addrelemlib.cpp | 34 ++----- src/amd/addrlib/core/addrlib.cpp | 11 ++- src/amd/addrlib/core/addrlib.h | 123 ++++++++++++++++++++++- src/amd/addrlib/core/addrlib1.cpp | 73 +++++++++----- src/amd/addrlib/core/addrlib2.cpp | 183 ++++------------------------------- src/amd/addrlib/core/addrlib2.h | 86 ++++++++-------- 7 files changed, 254 insertions(+), 270 deletions(-) (limited to 'src/amd/addrlib/core') diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h index 8f5f1bfb374..62f8ac61618 100644 --- a/src/amd/addrlib/core/addrcommon.h +++ b/src/amd/addrlib/core/addrcommon.h @@ -36,15 +36,9 @@ #include "addrinterface.h" -// ADDR_LNX_KERNEL_BUILD is for internal build -// Moved from addrinterface.h so __KERNEL__ is not needed any more -#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__)) - #include "lnx_common_defs.h" // ported from cmmqs -#elif !defined(__APPLE__) || defined(HAVE_TSERVER) - #include - #include - #include -#endif +#include +#include +#include #if BRAHMA_BUILD && !defined(DEBUG) #ifdef NDEBUG @@ -171,6 +165,8 @@ #endif // DEBUG //////////////////////////////////////////////////////////////////////////////////////////////////// +#define ADDR_C_ASSERT(__e) typedef char __ADDR_C_ASSERT__[(__e) ? 1 : -1] + namespace Addr { diff --git a/src/amd/addrlib/core/addrelemlib.cpp b/src/amd/addrlib/core/addrelemlib.cpp index 4bc46e0f585..c9e6da4729a 100644 --- a/src/amd/addrlib/core/addrelemlib.cpp +++ b/src/amd/addrlib/core/addrelemlib.cpp @@ -1271,6 +1271,9 @@ VOID ElemLib::RestoreSurfaceInfo( UINT_32 height; UINT_32 bpp; + BOOL_32 bBCnFormat = FALSE; + (void)bBCnFormat; + ADDR_ASSERT(pBpp != NULL); ADDR_ASSERT(pWidth != NULL && pHeight != NULL); @@ -1289,22 +1292,17 @@ VOID ElemLib::RestoreSurfaceInfo( break; case ADDR_PACKED_GBGR: case ADDR_PACKED_BGRG: - if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI) - { - originalBits = bpp / expandX; - } - else - { - originalBits = bpp; // 32-bit packed ==> 2 32-bit result - } + originalBits = bpp; // 32-bit packed ==> 2 32-bit result break; case ADDR_PACKED_BC1: // Fall through case ADDR_PACKED_BC4: originalBits = 64; + bBCnFormat = TRUE; break; case ADDR_PACKED_BC2: // Fall through case ADDR_PACKED_BC3: // Fall through case ADDR_PACKED_BC5: + bBCnFormat = TRUE; // fall through case ADDR_PACKED_ASTC: case ADDR_PACKED_ETC2_128BPP: @@ -1394,27 +1392,11 @@ UINT_32 ElemLib::GetBitsPerPixel( break; case ADDR_FMT_GB_GR: // treat as FMT_8_8 elemMode = ADDR_PACKED_GBGR; - if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI) - { - bpp = 32; - expandX = 2; - } - else - { - bpp = 16; - } + bpp = 16; break; case ADDR_FMT_BG_RG: // treat as FMT_8_8 elemMode = ADDR_PACKED_BGRG; - if (m_pAddrLib->GetChipFamily() >= ADDR_CHIP_FAMILY_AI) - { - bpp = 32; - expandX = 2; - } - else - { - bpp = 16; - } + bpp = 16; break; case ADDR_FMT_8_8_8_8: case ADDR_FMT_2_10_10_10: diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp index 65fd3451a0d..a6ac5ecf836 100644 --- a/src/amd/addrlib/core/addrlib.cpp +++ b/src/amd/addrlib/core/addrlib.cpp @@ -218,7 +218,16 @@ ADDR_E_RETURNCODE Lib::Create( } break; case CIASICIDGFXENGINE_ARCTICISLAND: - pLib = Gfx9HwlInit(&client); + switch (pCreateIn->chipFamily) + { + case FAMILY_AI: + case FAMILY_RV: + pLib = Gfx9HwlInit(&client); + break; + default: + ADDR_ASSERT_ALWAYS(); + break; + } break; default: ADDR_ASSERT_ALWAYS(); diff --git a/src/amd/addrlib/core/addrlib.h b/src/amd/addrlib/core/addrlib.h index 20700844272..8db65a61c87 100644 --- a/src/amd/addrlib/core/addrlib.h +++ b/src/amd/addrlib/core/addrlib.h @@ -38,11 +38,7 @@ #include "addrobject.h" #include "addrelemlib.h" -#if BRAHMA_BUILD -#include "amdgpu_id.h" -#else -#include "atiid.h" -#endif +#include "amdgpu_asic_addr.h" #ifndef CIASICIDGFXENGINE_R600 #define CIASICIDGFXENGINE_R600 0x00000006 @@ -126,6 +122,123 @@ enum BankSwapSize ADDR_BANKSWAP_1KB = 1024, }; +/** +**************************************************************************************************** +* @brief Enums that define max compressed fragments config +**************************************************************************************************** +*/ +enum NumMaxCompressedFragmentsConfig +{ + ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, + ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, + ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, + ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, +}; + +/** +**************************************************************************************************** +* @brief Enums that define num pipes config +**************************************************************************************************** +*/ +enum NumPipesConfig +{ + ADDR_CONFIG_1_PIPE = 0x00000000, + ADDR_CONFIG_2_PIPE = 0x00000001, + ADDR_CONFIG_4_PIPE = 0x00000002, + ADDR_CONFIG_8_PIPE = 0x00000003, + ADDR_CONFIG_16_PIPE = 0x00000004, + ADDR_CONFIG_32_PIPE = 0x00000005, + ADDR_CONFIG_64_PIPE = 0x00000006, +}; + +/** +**************************************************************************************************** +* @brief Enums that define num banks config +**************************************************************************************************** +*/ +enum NumBanksConfig +{ + ADDR_CONFIG_1_BANK = 0x00000000, + ADDR_CONFIG_2_BANK = 0x00000001, + ADDR_CONFIG_4_BANK = 0x00000002, + ADDR_CONFIG_8_BANK = 0x00000003, + ADDR_CONFIG_16_BANK = 0x00000004, +}; + +/** +**************************************************************************************************** +* @brief Enums that define num rb per shader engine config +**************************************************************************************************** +*/ +enum NumRbPerShaderEngineConfig +{ + ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, + ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, + ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, +}; + +/** +**************************************************************************************************** +* @brief Enums that define num shader engines config +**************************************************************************************************** +*/ +enum NumShaderEnginesConfig +{ + ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, + ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, + ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, + ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, +}; + +/** +**************************************************************************************************** +* @brief Enums that define pipe interleave size config +**************************************************************************************************** +*/ +enum PipeInterleaveSizeConfig +{ + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, + ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, + ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, +}; + +/** +**************************************************************************************************** +* @brief Enums that define row size config +**************************************************************************************************** +*/ +enum RowSizeConfig +{ + ADDR_CONFIG_1KB_ROW = 0x00000000, + ADDR_CONFIG_2KB_ROW = 0x00000001, + ADDR_CONFIG_4KB_ROW = 0x00000002, +}; + +/** +**************************************************************************************************** +* @brief Enums that define bank interleave size config +**************************************************************************************************** +*/ +enum BankInterleaveSizeConfig +{ + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, +}; + +/** +**************************************************************************************************** +* @brief Enums that define engine tile size config +**************************************************************************************************** +*/ +enum ShaderEngineTileSizeConfig +{ + ADDR_CONFIG_SE_TILE_16 = 0x00000000, + ADDR_CONFIG_SE_TILE_32 = 0x00000001, +}; + /** **************************************************************************************************** * @brief This class contains asic independent address lib functionalities diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index 548b24b7b69..c796a63436c 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -1281,36 +1281,54 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo( if (returnCode == ADDR_OK) { - pOut->bpp = ComputeHtileInfo(pIn->flags, - pIn->pitch, - pIn->height, - pIn->numSlices, - pIn->isLinear, - isWidth8, - isHeight8, - pIn->pTileInfo, - &pOut->pitch, - &pOut->height, - &pOut->htileBytes, - &pOut->macroWidth, - &pOut->macroHeight, - &pOut->sliceSize, - &pOut->baseAlign); - - if (pIn->flags.tcCompatible && (pIn->numSlices > 1)) + if (pIn->flags.tcCompatible) { - pOut->sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8); - - const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes; + const UINT_32 sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8); + const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes; - if ((pOut->sliceSize % align) == 0) + if (pIn->numSlices > 1) { - pOut->sliceInterleaved = FALSE; + const UINT_32 surfBytes = (sliceSize * pIn->numSlices); + + pOut->sliceSize = sliceSize; + pOut->htileBytes = pIn->flags.skipTcCompatSizeAlign ? + surfBytes : PowTwoAlign(surfBytes, align); + pOut->sliceInterleaved = ((sliceSize % align) != 0) ? TRUE : FALSE; } else { - pOut->sliceInterleaved = TRUE; + pOut->sliceSize = pIn->flags.skipTcCompatSizeAlign ? + sliceSize : PowTwoAlign(sliceSize, align); + pOut->htileBytes = pOut->sliceSize; + pOut->sliceInterleaved = FALSE; } + + pOut->nextMipLevelCompressible = ((sliceSize % align) == 0) ? TRUE : FALSE; + + pOut->pitch = pIn->pitch; + pOut->height = pIn->height; + pOut->baseAlign = align; + pOut->macroWidth = 0; + pOut->macroHeight = 0; + pOut->bpp = 32; + } + else + { + pOut->bpp = ComputeHtileInfo(pIn->flags, + pIn->pitch, + pIn->height, + pIn->numSlices, + pIn->isLinear, + isWidth8, + isHeight8, + pIn->pTileInfo, + &pOut->pitch, + &pOut->height, + &pOut->htileBytes, + &pOut->macroWidth, + &pOut->macroHeight, + &pOut->sliceSize, + &pOut->baseAlign); } } } @@ -2162,6 +2180,8 @@ VOID Lib::HwlComputeXmaskCoordFromAddr( { UINT_32 pipe; UINT_32 numPipes; + UINT_32 numGroupBits; + (void)numGroupBits; UINT_32 numPipeBits; UINT_32 macroTilePitch; UINT_32 macroTileHeight; @@ -2204,6 +2224,7 @@ VOID Lib::HwlComputeXmaskCoordFromAddr( // // Compute the number of group and pipe bits. // + numGroupBits = Log2(m_pipeInterleaveBytes); numPipeBits = Log2(numPipes); UINT_32 groupBits = 8 * m_pipeInterleaveBytes; @@ -3504,6 +3525,10 @@ VOID Lib::ComputeMipLevel( ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure ) const { + // Check if HWL has handled + BOOL_32 hwlHandled = FALSE; + (void)hwlHandled; + if (ElemLib::IsBlockCompressed(pIn->format)) { if (pIn->mipLevel == 0) @@ -3517,7 +3542,7 @@ VOID Lib::ComputeMipLevel( } } - HwlComputeMipLevel(pIn); + hwlHandled = HwlComputeMipLevel(pIn); } /** diff --git a/src/amd/addrlib/core/addrlib2.cpp b/src/amd/addrlib/core/addrlib2.cpp index 57505d35af5..ddaf597f9dd 100644 --- a/src/amd/addrlib/core/addrlib2.cpp +++ b/src/amd/addrlib/core/addrlib2.cpp @@ -355,6 +355,11 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoord( { returnCode = ComputeSurfaceAddrFromCoordTiled(&localIn, pOut); } + + if (returnCode == ADDR_OK) + { + pOut->prtBlockIndex = static_cast(pOut->addr / (64 * 1024)); + } } return returnCode; @@ -460,8 +465,7 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo( */ ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord( const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure - ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure - ) const + ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure { ADDR_E_RETURNCODE returnCode; @@ -492,8 +496,7 @@ ADDR_E_RETURNCODE Lib::ComputeHtileAddrFromCoord( */ ADDR_E_RETURNCODE Lib::ComputeHtileCoordFromAddr( const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, ///< [in] input structure - ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut ///< [out] output structure - ) const + ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) ///< [out] output structure { ADDR_E_RETURNCODE returnCode; @@ -560,8 +563,7 @@ ADDR_E_RETURNCODE Lib::ComputeCmaskInfo( */ ADDR_E_RETURNCODE Lib::ComputeCmaskAddrFromCoord( const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure - ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure - ) const + ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure { ADDR_E_RETURNCODE returnCode; @@ -780,8 +782,7 @@ ADDR_E_RETURNCODE Lib::ComputeDccInfo( */ ADDR_E_RETURNCODE Lib::ComputeDccAddrFromCoord( const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, ///< [in] input structure - ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut ///< [out] output structure - ) const + ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) ///< [out] output structure { ADDR_E_RETURNCODE returnCode; @@ -1047,77 +1048,7 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfoLinear( ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure ) const { - ADDR_E_RETURNCODE returnCode = ADDR_OK; - - UINT_32 pitch = 0; - UINT_32 actualHeight = 0; - UINT_32 elementBytes = pIn->bpp >> 3; - const UINT_32 alignment = pIn->flags.prt ? PrtAlignment : 256; - - if (IsTex1d(pIn->resourceType)) - { - if (pIn->height > 1) - { - returnCode = ADDR_INVALIDPARAMS; - } - else - { - const UINT_32 pitchAlignInElement = alignment / elementBytes; - pitch = PowTwoAlign(pIn->width, pitchAlignInElement); - actualHeight = pIn->numMipLevels; - - if (pIn->flags.prt == FALSE) - { - returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement, - &pitch, &actualHeight); - } - - if (returnCode == ADDR_OK) - { - if (pOut->pMipInfo != NULL) - { - for (UINT_32 i = 0; i < pIn->numMipLevels; i++) - { - pOut->pMipInfo[i].offset = pitch * elementBytes * i; - pOut->pMipInfo[i].pitch = pitch; - pOut->pMipInfo[i].height = 1; - pOut->pMipInfo[i].depth = 1; - } - } - } - } - } - else - { - returnCode = ComputeSurfaceLinearPadding(pIn, &pitch, &actualHeight, pOut->pMipInfo); - } - - if ((pitch == 0) || (actualHeight == 0)) - { - returnCode = ADDR_INVALIDPARAMS; - } - - if (returnCode == ADDR_OK) - { - pOut->pitch = pitch; - pOut->height = pIn->height; - pOut->numSlices = pIn->numSlices; - pOut->mipChainPitch = pitch; - pOut->mipChainHeight = actualHeight; - pOut->mipChainSlice = pOut->numSlices; - pOut->epitchIsHeight = (pIn->numMipLevels > 1) ? TRUE : FALSE; - pOut->sliceSize = static_cast(pOut->pitch) * actualHeight * elementBytes; - pOut->surfSize = pOut->sliceSize * pOut->numSlices; - pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment; - pOut->blockWidth = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? 1 : (256 * 8 / pIn->bpp); - pOut->blockHeight = 1; - pOut->blockSlices = 1; - } - - // Post calculation validate - ADDR_ASSERT(pOut->sliceSize > 0); - - return returnCode; + return HwlComputeSurfaceInfoLinear(pIn, pOut); } /** @@ -1170,6 +1101,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear( { ADDR2_COMPUTE_SURFACE_INFO_INPUT localIn = {0}; ADDR2_COMPUTE_SURFACE_INFO_OUTPUT localOut = {0}; + ADDR2_MIP_INFO mipInfo[MaxMipLevels]; + localIn.bpp = pIn->bpp; localIn.flags = pIn->flags; localIn.width = Max(pIn->unalignedWidth, 1u); @@ -1177,32 +1110,21 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceAddrFromCoordLinear( localIn.numSlices = Max(pIn->numSlices, 1u); localIn.numMipLevels = Max(pIn->numMipLevels, 1u); localIn.resourceType = pIn->resourceType; + if (localIn.numMipLevels <= 1) { localIn.pitchInElement = pIn->pitchInElement; } + + localOut.pMipInfo = mipInfo; + returnCode = ComputeSurfaceInfoLinear(&localIn, &localOut); if (returnCode == ADDR_OK) { - UINT_32 elementBytes = pIn->bpp >> 3; - UINT_64 sliceOffsetInSurf = localOut.sliceSize * pIn->slice; - UINT_64 mipOffsetInSlice = 0; - UINT_64 offsetInMip = 0; - - if (IsTex1d(pIn->resourceType)) - { - offsetInMip = static_cast(pIn->x) * elementBytes; - mipOffsetInSlice = static_cast(pIn->mipId) * localOut.pitch * elementBytes; - } - else - { - UINT_64 mipStartHeight = SumGeo(localIn.height, pIn->mipId); - mipOffsetInSlice = static_cast(mipStartHeight) * localOut.pitch * elementBytes; - offsetInMip = (pIn->y * localOut.pitch + pIn->x) * elementBytes; - } - - pOut->addr = sliceOffsetInSurf + mipOffsetInSlice + offsetInMip; + pOut->addr = (localOut.sliceSize * pIn->slice) + + mipInfo[pIn->mipId].offset + + (pIn->y * mipInfo[pIn->mipId].pitch + pIn->x) * (pIn->bpp >> 3); pOut->bitPosition = 0; } else @@ -1398,73 +1320,6 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceCoordFromAddrTiled( return returnCode; } -/** -************************************************************************************************************************ -* Lib::ComputeSurfaceInfoLinear -* -* @brief -* Internal function to calculate padding for linear swizzle 2D/3D surface -* -* @return -* N/A -************************************************************************************************************************ -*/ -ADDR_E_RETURNCODE Lib::ComputeSurfaceLinearPadding( - const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input srtucture - UINT_32* pMipmap0PaddedWidth, ///< [out] padded width in element - UINT_32* pSlice0PaddedHeight, ///< [out] padded height for HW - ADDR2_MIP_INFO* pMipInfo ///< [out] per mip information - ) const -{ - ADDR_E_RETURNCODE returnCode = ADDR_OK; - - UINT_32 elementBytes = pIn->bpp >> 3; - UINT_32 pitchAlignInElement = 0; - - if (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) - { - ADDR_ASSERT(pIn->numMipLevels <= 1); - ADDR_ASSERT(pIn->numSlices <= 1); - pitchAlignInElement = 1; - } - else - { - pitchAlignInElement = (256 / elementBytes); - } - - UINT_32 mipChainWidth = PowTwoAlign(pIn->width, pitchAlignInElement); - UINT_32 slice0PaddedHeight = pIn->height; - - returnCode = ApplyCustomizedPitchHeight(pIn, elementBytes, pitchAlignInElement, - &mipChainWidth, &slice0PaddedHeight); - - if (returnCode == ADDR_OK) - { - UINT_32 mipChainHeight = 0; - UINT_32 mipHeight = pIn->height; - - for (UINT_32 i = 0; i < pIn->numMipLevels; i++) - { - if (pMipInfo != NULL) - { - pMipInfo[i].offset = mipChainWidth * mipChainHeight * elementBytes; - pMipInfo[i].pitch = mipChainWidth; - pMipInfo[i].height = mipHeight; - pMipInfo[i].depth = 1; - } - - mipChainHeight += mipHeight; - mipHeight = RoundHalf(mipHeight); - mipHeight = Max(mipHeight, 1u); - } - - *pMipmap0PaddedWidth = mipChainWidth; - *pSlice0PaddedHeight = (pIn->numMipLevels > 1) ? mipChainHeight : slice0PaddedHeight; - } - - return returnCode; -} - /** ************************************************************************************************************************ * Lib::ComputeBlockDimensionForSurf diff --git a/src/amd/addrlib/core/addrlib2.h b/src/amd/addrlib/core/addrlib2.h index e98fddcd2d0..bea2a485a61 100644 --- a/src/amd/addrlib/core/addrlib2.h +++ b/src/amd/addrlib/core/addrlib2.h @@ -103,63 +103,63 @@ public: // For data surface ADDR_E_RETURNCODE ComputeSurfaceInfo( const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, - ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; + ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; + ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( - const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, - ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; + const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, + ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; // For HTile ADDR_E_RETURNCODE ComputeHtileInfo( const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, - ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; + ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( - const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const; + const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( - const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, - ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const; + const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, + ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); // For CMask ADDR_E_RETURNCODE ComputeCmaskInfo( const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, - ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; + ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( - const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const; + const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( - const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, - ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; + const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, + ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; // For FMask ADDR_E_RETURNCODE ComputeFmaskInfo( - const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, - ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); + const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, + ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( - const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; + const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( - const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, - ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; + const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, + ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; // For DCC key ADDR_E_RETURNCODE ComputeDccInfo( const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, - ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; + ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; ADDR_E_RETURNCODE ComputeDccAddrFromCoord( - const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const; + const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); // Misc ADDR_E_RETURNCODE ComputePipeBankXor( @@ -197,6 +197,8 @@ protected: static const UINT_32 PrtAlignment = 64 * 1024; static const UINT_32 MaxMacroBits = 20; + static const UINT_32 MaxMipLevels = 16; + // Checking block size BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const { @@ -402,32 +404,32 @@ protected: } virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord( - const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const + const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) { ADDR_NOT_IMPLEMENTED(); return ADDR_NOTSUPPORTED; } virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( - const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const + const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) { ADDR_NOT_IMPLEMENTED(); return ADDR_NOTSUPPORTED; } virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( - const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, - ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const + const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, + ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) { ADDR_NOT_IMPLEMENTED(); return ADDR_NOTSUPPORTED; } virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( - const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, - ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const + const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, + ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) { ADDR_NOT_IMPLEMENTED(); return ADDR_NOTSUPPORTED; @@ -532,6 +534,14 @@ protected: return ADDR_NOTIMPLEMENTED; } + virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( + const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, + ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const + { + ADDR_NOT_IMPLEMENTED(); + return ADDR_NOTIMPLEMENTED; + } + virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const @@ -565,12 +575,6 @@ protected: const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; - ADDR_E_RETURNCODE ComputeSurfaceLinearPadding( - const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, - UINT_32* pMipmap0PaddedWidth, - UINT_32* pSlice0PaddedHeight, - ADDR2_MIP_INFO* pMipInfo = NULL) const; - ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; @@ -757,10 +761,10 @@ protected: ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, - UINT_32 elementBytes, - UINT_32 pitchAlignInElement, - UINT_32* pPitch, - UINT_32* pHeight) const; + UINT_32 elementBytes, + UINT_32 pitchAlignInElement, + UINT_32* pPitch, + UINT_32* pHeight) const; VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; -- cgit v1.2.3