From aa739dff86e4adb0b746568f7608bb57f90ceb6f Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Thu, 29 Oct 2015 17:30:35 -0700 Subject: i965/skl: Add GT4 PCI IDs Like other gen8+ hardware, the hardware automatically scales up thread counts. We must be careful about the URB sizes since GT4 adds another slice. One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a real bug since the URB size will be wrong. Because this patch is simply meant to add the missing IDs, that will be fixed in a later patch. v2: No longer relevant. v3: Update the wm thread count to support GT4. The WM thread count is used to determine the maximum scratch space required. Currently the code always allocates the maximum amount even though lower GT SKUs require less. The formula is threads_per_psd * subslices_per_slice * slices Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Jordan Justen Signed-off-by: Ben Widawsky (cherry picked from commit 7cbd6608f544591bc6aadf48877608b30a78ccb8) --- include/pci_ids/i965_pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/pci_ids') diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 8a425999429..626064a75c5 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -124,6 +124,10 @@ CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F") CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3") CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3") CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3") +CHIPSET(0x1932, skl_gt4, "Intel(R) Skylake GT4") +CHIPSET(0x193A, skl_gt4, "Intel(R) Skylake GT4") +CHIPSET(0x193B, skl_gt4, "Intel(R) Skylake GT4") +CHIPSET(0x193D, skl_gt4, "Intel(R) Skylake GT4") CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") -- cgit v1.2.3