From ff1a015ca86ed4ea2ca3fdd49ed9daaae19359a2 Mon Sep 17 00:00:00 2001
From: Brian Paul <brian.paul@tungstengraphics.com>
Date: Fri, 2 Apr 2004 17:27:46 +0000
Subject: Implement ARB_f_p KIL correctly.

---
 src/mesa/shader/nvfragparse.c  |  4 ++--
 src/mesa/shader/nvfragprog.h   |  3 ++-
 src/mesa/swrast/s_nvfragprog.c | 11 ++++++++++-
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/mesa/shader/nvfragparse.c b/src/mesa/shader/nvfragparse.c
index b742ff0a32d..bdc2c7ef94a 100644
--- a/src/mesa/shader/nvfragparse.c
+++ b/src/mesa/shader/nvfragparse.c
@@ -95,7 +95,7 @@ static const struct instruction_pattern Instructions[] = {
    { "EX2", FP_OPCODE_DP4, INPUT_1S, OUTPUT_S, _R | _H |      _C | _S },
    { "FLR", FP_OPCODE_FLR, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
    { "FRC", FP_OPCODE_FRC, INPUT_1V, OUTPUT_V, _R | _H | _X | _C | _S },
-   { "KIL", FP_OPCODE_KIL, INPUT_CC, OUTPUT_NONE, 0                   },
+   { "KIL", FP_OPCODE_KIL_NV, INPUT_CC, OUTPUT_NONE, 0                   },
    { "LG2", FP_OPCODE_LG2, INPUT_1S, OUTPUT_S, _R | _H |      _C | _S },
    { "LIT", FP_OPCODE_LIT, INPUT_1V, OUTPUT_V, _R | _H |      _C | _S },
    { "LRP", FP_OPCODE_LRP, INPUT_3V, OUTPUT_V, _R | _H | _X | _C | _S },
@@ -1291,7 +1291,7 @@ Parse_InstructionSequence(struct parse_state *parseState,
                RETURN_ERROR1("Expected ,");
          }
          else if (instMatch.outputs == OUTPUT_NONE) {
-            ASSERT(instMatch.opcode == FP_OPCODE_KIL);
+            ASSERT(instMatch.opcode == FP_OPCODE_KIL_NV);
             /* This is a little weird, the cond code info is in the dest register */
             if (!Parse_CondCodeMask(parseState, &inst->DstReg))
                RETURN_ERROR;
diff --git a/src/mesa/shader/nvfragprog.h b/src/mesa/shader/nvfragprog.h
index e83827d1a16..53f4bf9905c 100644
--- a/src/mesa/shader/nvfragprog.h
+++ b/src/mesa/shader/nvfragprog.h
@@ -75,7 +75,8 @@ enum fp_opcode {
    FP_OPCODE_EX2,
    FP_OPCODE_FLR,
    FP_OPCODE_FRC,
-   FP_OPCODE_KIL,
+   FP_OPCODE_KIL_NV,         /* NV_f_p only */
+   FP_OPCODE_KIL,            /* ARB_f_p only */
    FP_OPCODE_LG2,
    FP_OPCODE_LIT,
    FP_OPCODE_LRP,
diff --git a/src/mesa/swrast/s_nvfragprog.c b/src/mesa/swrast/s_nvfragprog.c
index c262618dda0..036c1870d1f 100644
--- a/src/mesa/swrast/s_nvfragprog.c
+++ b/src/mesa/swrast/s_nvfragprog.c
@@ -763,7 +763,7 @@ execute_program( GLcontext *ctx,
                store_vector4( inst, machine, result );
             }
             break;
-         case FP_OPCODE_KIL:
+         case FP_OPCODE_KIL_NV: /* NV_f_p only */
             {
                const GLuint *swizzle = inst->DstReg.CondSwizzle;
                const GLuint condMask = inst->DstReg.CondMask;
@@ -775,6 +775,15 @@ execute_program( GLcontext *ctx,
                }
             }
             break;
+         case FP_OPCODE_KIL: /* ARB_f_p only */
+            {
+               GLfloat a[4];
+               fetch_vector4( ctx, &inst->SrcReg[0], machine, program, a );
+               if (a[0] < 0.0F || a[1] < 0.0F || a[2] < 0.0F || a[3] < 0.0F) {
+                  return GL_FALSE;
+               }
+            }
+            break;
          case FP_OPCODE_LG2:  /* log base 2 */
             {
                GLfloat a[4], result[4];
-- 
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