From f91e4d2c9d714bb7d667956cd93f216c18a434f4 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 8 Apr 2013 16:41:01 +0200 Subject: radeon/winsys: add uvd ring support to winsys v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Separated from UVD patch for clarity. v2: sync with next tree for 3.10 v3: as pointed out by Andreas Bool check for drm minor >= 32 http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Andreas Boll --- src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 11 +++++++++++ src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 17 +++++++++++++++++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 +++ 3 files changed, 31 insertions(+) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index aa7e295e21c..720e0864d19 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -94,6 +94,10 @@ #define RADEON_CS_RING_DMA 2 #endif +#ifndef RADEON_CS_RING_UVD +#define RADEON_CS_RING_UVD 3 +#endif + #ifndef RADEON_CS_END_OF_FRAME #define RADEON_CS_END_OF_FRAME 0x04 #endif @@ -490,6 +494,13 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags) cs->cst->flags[0] |= RADEON_CS_USE_VM; } break; + + case RING_UVD: + cs->cst->flags[0] = 0; + cs->cst->flags[1] = RADEON_CS_RING_UVD; + cs->cst->cs.num_chunks = 3; + break; + default: case RING_GFX: cs->cst->flags[0] = 0; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index d1f76431b19..e25ab9be7be 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -90,6 +90,14 @@ #define RADEON_INFO_TIMESTAMP 0x11 #endif +#ifndef RADEON_INFO_RING_WORKING +#define RADEON_INFO_RING_WORKING 0x15 +#endif + +#ifndef RADEON_CS_RING_UVD +#define RADEON_CS_RING_UVD 3 +#endif + static struct util_hash_table *fd_tab = NULL; /* Enable/disable feature access for one command stream. @@ -323,6 +331,15 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) ws->info.r600_has_dma = TRUE; } + /* Check for UVD */ + ws->info.has_uvd = FALSE; + if (ws->info.drm_minor >= 32) { + uint32_t value = RADEON_CS_RING_UVD; + if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, + "UVD Ring working", &value)) + ws->info.has_uvd = value; + } + /* Get GEM info. */ retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index 36f1f8e7ec4..e343188d3b7 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -142,6 +142,7 @@ enum chip_class { enum ring_type { RING_GFX = 0, RING_DMA, + RING_UVD, RING_LAST, }; @@ -170,6 +171,8 @@ struct radeon_info { uint32_t drm_minor; uint32_t drm_patchlevel; + boolean has_uvd; + uint32_t r300_num_gb_pipes; uint32_t r300_num_z_pipes; -- cgit v1.2.3