From f1f9794118008bcdc13d93ee709022d21cc4156d Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 31 Jan 2017 15:06:56 -0800 Subject: anv: Flush render cache before STATE_BASE_ADDRESS on gen7 We had no good reason for *not* doing this on gen7 before but we didn't know it was needed. Recently, when trying update to Vulkan CTS version 1.0.2 in our CI system, Mark discovered GPU hangs on Haswell that appear to be STATE_BASE_ADDRESS related. This commit fixes them. Reported-by: Mark Janes Reviewed-by: Kenneth Graunke Cc: "13.0 17.0" --- src/intel/vulkan/genX_cmd_buffer.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index d93d3770554..d0e76e3db67 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -55,8 +55,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) { struct anv_device *device = cmd_buffer->device; -/* XXX: Do we need this on more than just BDW? */ -#if (GEN_GEN >= 8) /* Emit a render target cache flush. * * This isn't documented anywhere in the PRM. However, it seems to be @@ -67,7 +65,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { pc.RenderTargetCacheFlushEnable = true; } -#endif anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 }; -- cgit v1.2.3