From e1523b34c2aeebdf2952bfad4f0e40326fb2cc7c Mon Sep 17 00:00:00 2001
From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 4 Jun 2020 10:35:23 +0200
Subject: aco: fix sign-extend 8-bit subgroup operations on GFX6-GFX7
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SDWA is GFX8+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5327>
---
 src/amd/compiler/aco_lower_to_hw_instr.cpp | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp
index a278b66ce82..480dd32e6ce 100644
--- a/src/amd/compiler/aco_lower_to_hw_instr.cpp
+++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp
@@ -568,15 +568,27 @@ void emit_reduction(lower_context *ctx, aco_opcode op, ReduceOp reduce_op, unsig
    }
 
    if (src.regClass() == v1b) {
-      aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
-      sdwa->operands[0] = Operand(PhysReg{tmp}, v1);
-      sdwa->definitions[0] = Definition(PhysReg{tmp}, v1);
-      if (reduce_op == imin8 || reduce_op == imax8)
-         sdwa->sel[0] = sdwa_sbyte;
-      else
-         sdwa->sel[0] = sdwa_ubyte;
-      sdwa->dst_sel = sdwa_udword;
-      bld.insert(std::move(sdwa));
+      if (ctx->program->chip_class >= GFX8) {
+         aco_ptr<SDWA_instruction> sdwa{create_instruction<SDWA_instruction>(aco_opcode::v_mov_b32, asSDWA(Format::VOP1), 1, 1)};
+         sdwa->operands[0] = Operand(PhysReg{tmp}, v1);
+         sdwa->definitions[0] = Definition(PhysReg{tmp}, v1);
+         if (reduce_op == imin8 || reduce_op == imax8)
+            sdwa->sel[0] = sdwa_sbyte;
+         else
+            sdwa->sel[0] = sdwa_ubyte;
+         sdwa->dst_sel = sdwa_udword;
+         bld.insert(std::move(sdwa));
+      } else {
+         aco_opcode opcode;
+
+         if (reduce_op == imin8 || reduce_op == imax8)
+            opcode = aco_opcode::v_bfe_i32;
+         else
+            opcode = aco_opcode::v_bfe_u32;
+
+         bld.vop3(opcode, Definition(PhysReg{tmp}, v1),
+                  Operand(PhysReg{tmp}, v1), Operand(0u), Operand(8u));
+      }
    } else if (src.regClass() == v2b) {
       if (ctx->program->chip_class >= GFX10 &&
           (reduce_op == iadd16 || reduce_op == imax16 ||
-- 
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