From cd5d02bf51af370233f35604a69d07e70db11eaf Mon Sep 17 00:00:00 2001 From: Marek Olšák <maraeo@gmail.com> Date: Sat, 25 Feb 2012 02:49:13 +0100 Subject: r600g: make some scissor regs invariant on evergreen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We only need one scissor for the framebuffer. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> --- src/gallium/drivers/r600/evergreen_hw_context.c | 10 --------- src/gallium/drivers/r600/evergreen_state.c | 28 ++++++++++++++----------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index f35ee23465b..352aeb8b4a1 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -52,9 +52,6 @@ static const struct r600_reg evergreen_context_reg_list[] = { {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0}, {GROUP_FORCE_NEW_BLOCK, 0, 0}, - {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, - {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0}, {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028044_DB_STENCIL_INFO, 0, 0}, @@ -78,8 +75,6 @@ static const struct r600_reg evergreen_context_reg_list[] = { {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, {R_028238_CB_TARGET_MASK, 0, 0}, {R_02823C_CB_SHADER_MASK, 0, 0}, - {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, - {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, {R_028350_SX_MISC, 0, 0}, @@ -324,9 +319,6 @@ static const struct r600_reg cayman_context_reg_list[] = { {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0}, {GROUP_FORCE_NEW_BLOCK, 0, 0}, - {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, - {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, - {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0}, {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028044_DB_STENCIL_INFO, 0, 0}, @@ -350,8 +342,6 @@ static const struct r600_reg cayman_context_reg_list[] = { {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0}, {R_028238_CB_TARGET_MASK, 0, 0}, {R_02823C_CB_SHADER_MASK, 0, 0}, - {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, - {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, {R_028350_SX_MISC, 0, 0}, diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index b8d6e54af76..65becc41b9f 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1639,18 +1639,6 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br); - r600_pipe_state_add_reg(rstate, - R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028244_PA_SC_GENERIC_SCISSOR_BR, br, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, - NULL, 0); - r600_pipe_state_add_reg(rstate, - R_028034_PA_SC_SCREEN_SCISSOR_BR, br, - NULL, 0); r600_pipe_state_add_reg(rstate, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, NULL, 0); @@ -1872,6 +1860,14 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */ r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ + r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); + r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ + r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ + + r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); + r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ + r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ + r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO)); r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO)); r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); @@ -2346,6 +2342,14 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0); + r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); + r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ + r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ + + r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); + r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ + r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ + r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO)); r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO)); r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); -- cgit v1.2.3