From b8c06a961c903cfae48bb3dc2e64a51796bd8a5a Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 4 Apr 2018 10:55:43 +0200 Subject: radv: don't use the SPI barrier management bug workaround Ported from RadeonSI. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_pipeline.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 5a44efb78b3..89a643a1b10 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1274,6 +1274,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta static void si_multiwave_lds_size_workaround(struct radv_device *device, unsigned *lds_size) { + /* If tessellation is all offchip and on-chip GS isn't used, this + * workaround is not needed. + */ + return; + /* SPI barrier management bug: * Make sure we have at least 4k of LDS in use to avoid the bug. * It applies to workgroup sizes of more than one wavefront. -- cgit v1.2.3