From 9b5eda85448fde9d923d33c73888dd9ac23289c4 Mon Sep 17 00:00:00 2001 From: Chris Forbes <chrisf@ijw.co.nz> Date: Thu, 9 Jan 2014 09:56:16 +1300 Subject: i965: Add masks for more SURFACE_STATE fields Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> --- src/mesa/drivers/dri/i965/brw_defines.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index fe5a1475bd6..bcc7d6ad97b 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -541,7 +541,9 @@ #define GEN7_SURFACE_MSFMT_MSS (0 << 6) #define GEN7_SURFACE_MSFMT_DEPTH_STENCIL (1 << 6) #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT 18 +#define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK INTEL_MASK(28, 18) #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT 7 +#define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK INTEL_MASK(17, 7) /* Surface state DW5 */ #define BRW_SURFACE_X_OFFSET_SHIFT 25 -- cgit v1.2.3