From 9b00fa9ac24cb5c2e8740dac4b8c2c28e6b861f5 Mon Sep 17 00:00:00 2001
From: Brian <brian@yutani.localnet.net>
Date: Fri, 15 Dec 2006 15:36:09 -0700
Subject: code movement

---
 src/mesa/shader/slang/slang_codegen.c | 92 +++++++++++++++++------------------
 src/mesa/shader/slang/slang_emit.c    |  5 +-
 2 files changed, 47 insertions(+), 50 deletions(-)

diff --git a/src/mesa/shader/slang/slang_codegen.c b/src/mesa/shader/slang/slang_codegen.c
index acca05df805..611b6145f57 100644
--- a/src/mesa/shader/slang/slang_codegen.c
+++ b/src/mesa/shader/slang/slang_codegen.c
@@ -52,6 +52,52 @@ static slang_ir_node *
 slang_assemble_operation(slang_assemble_ctx * A, slang_operation *oper);
 
 
+/**
+ * Map "_asm foo" to IR_FOO, etc.
+ */
+typedef struct
+{
+   const char *Name;
+   slang_ir_opcode Opcode;
+   GLuint HaveRetValue, NumParams;
+} slang_asm_info;
+
+
+static slang_asm_info AsmInfo[] = {
+   /* vec4 binary op */
+   { "vec4_add", IR_ADD, 1, 2 },
+   { "vec4_multiply", IR_MUL, 1, 2 },
+   { "vec4_dot", IR_DOT4, 1, 2 },
+   { "vec3_dot", IR_DOT3, 1, 2 },
+   { "vec3_cross", IR_CROSS, 1, 2 },
+   { "vec4_min", IR_MIN, 1, 2 },
+   { "vec4_max", IR_MAX, 1, 2 },
+   { "vec4_seq", IR_SEQ, 1, 2 },
+   { "vec4_sge", IR_SGE, 1, 2 },
+   { "vec4_sgt", IR_SGT, 1, 2 },
+   /* vec4 unary */
+   { "vec4_floor", IR_FLOOR, 1, 1 },
+   { "vec4_frac", IR_FRAC, 1, 1 },
+   { "vec4_abs", IR_ABS, 1, 1 },
+   /* float binary op */
+   { "float_add", IR_ADD, 1, 2 },
+   { "float_subtract", IR_SUB, 1, 2 },
+   { "float_multiply", IR_MUL, 1, 2 },
+   { "float_divide", IR_DIV, 1, 2 },
+   { "float_power", IR_POW, 1, 2 },
+   /* unary op */
+   { "int_to_float", IR_I_TO_F, 1, 1 },
+   { "float_exp", IR_EXP, 1, 1 },
+   { "float_exp2", IR_EXP2, 1, 1 },
+   { "float_log2", IR_LOG2, 1, 1 },
+   { "float_rsq", IR_RSQ, 1, 1 },
+   { "float_rcp", IR_RCP, 1, 1 },
+   { "float_sine", IR_SIN, 1, 1 },
+   { "float_cosine", IR_COS, 1, 1 },
+   { NULL, IR_NOP, 0, 0 }
+};
+
+
 
 static slang_ir_node *
 new_node(slang_ir_opcode op, slang_ir_node *left, slang_ir_node *right)
@@ -739,52 +785,6 @@ slang_assemble_function_call(slang_assemble_ctx *A, slang_function *fun,
 }
 
 
-/**
- * Map "_asm foo" to IR_FOO, etc.
- */
-typedef struct
-{
-   const char *Name;
-   slang_ir_opcode Opcode;
-   GLuint HaveRetValue, NumParams;
-} slang_asm_info;
-
-
-static slang_asm_info AsmInfo[] = {
-   /* vec4 binary op */
-   { "vec4_add", IR_ADD, 1, 2 },
-   { "vec4_multiply", IR_MUL, 1, 2 },
-   { "vec4_dot", IR_DOT4, 1, 2 },
-   { "vec3_dot", IR_DOT3, 1, 2 },
-   { "vec3_cross", IR_CROSS, 1, 2 },
-   { "vec4_min", IR_MIN, 1, 2 },
-   { "vec4_max", IR_MAX, 1, 2 },
-   { "vec4_seq", IR_SEQ, 1, 2 },
-   { "vec4_sge", IR_SGE, 1, 2 },
-   { "vec4_sgt", IR_SGT, 1, 2 },
-   /* vec4 unary */
-   { "vec4_floor", IR_FLOOR, 1, 1 },
-   { "vec4_frac", IR_FRAC, 1, 1 },
-   { "vec4_abs", IR_ABS, 1, 1 },
-   /* float binary op */
-   { "float_add", IR_ADD, 1, 2 },
-   { "float_subtract", IR_SUB, 1, 2 },
-   { "float_multiply", IR_MUL, 1, 2 },
-   { "float_divide", IR_DIV, 1, 2 },
-   { "float_power", IR_POW, 1, 2 },
-   /* unary op */
-   { "int_to_float", IR_I_TO_F, 1, 1 },
-   { "float_exp", IR_EXP, 1, 1 },
-   { "float_exp2", IR_EXP2, 1, 1 },
-   { "float_log2", IR_LOG2, 1, 1 },
-   { "float_rsq", IR_RSQ, 1, 1 },
-   { "float_rcp", IR_RCP, 1, 1 },
-   { "float_sine", IR_SIN, 1, 1 },
-   { "float_cosine", IR_COS, 1, 1 },
-   { NULL, IR_NOP, 0, 0 }
-};
-
-
 static slang_asm_info *
 slang_find_asm_info(const char *name)
 {
diff --git a/src/mesa/shader/slang/slang_emit.c b/src/mesa/shader/slang/slang_emit.c
index 4f7a9dd309c..8b95b94698b 100644
--- a/src/mesa/shader/slang/slang_emit.c
+++ b/src/mesa/shader/slang/slang_emit.c
@@ -982,7 +982,6 @@ gen(slang_gen_context *gc, slang_ir_node *n, struct gl_program *prog)
       else
 #endif
       {
-#if 1
          if (n->Children[0]->Store->Size > 4) {
             /* move matrix/struct etc */
             slang_ir_storage dstStore = *n->Children[0]->Store;
@@ -1003,9 +1002,7 @@ gen(slang_gen_context *gc, slang_ir_node *n, struct gl_program *prog)
                size -= 4;
             }
          }
-         else
-#endif
-         {
+         else {
             inst = new_instruction(prog, OPCODE_MOV);
             storage_to_dst_reg(&inst->DstReg, n->Children[0]->Store, n->Writemask);
             storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Store,
-- 
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