From 97d3d25e1ce137557ebac82410e57219f92c0191 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 6 Sep 2012 18:14:22 +0200 Subject: radeon/llvm: Match AMDGPUfract on SI. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michel Dänzer Reviewed-by: Tom Stellard --- src/gallium/drivers/radeon/SIInstructions.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 4b76dad0eec..b221d6d07ff 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -524,7 +524,9 @@ defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; //defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; //defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; //defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; -defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", []>; +defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", + [(set VReg_32:$dst, (AMDGPUfract AllReg_32:$src0))] +>; defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>; defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", []>; defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", -- cgit v1.2.3